Patents by Inventor Dae-Hwan Kang
Dae-Hwan Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10497751Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.Type: GrantFiled: April 27, 2018Date of Patent: December 3, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyu-Rie Sim, Gwan-Hyeob Koh, Dae-Hwan Kang
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Publication number: 20190189692Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: ApplicationFiled: February 21, 2019Publication date: June 20, 2019Inventors: Ji-hyun JEONG, Gwan-hyeob KOH, Dae-hwan KANG
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Publication number: 20190181342Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction.Type: ApplicationFiled: February 15, 2019Publication date: June 13, 2019Inventors: KWANG-WOO LEE, DAE-HWAN KANG, GWAN-HYEOB KOH
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Publication number: 20190140022Abstract: A memory device includes a first word line extending in a first direction on a substrate, a first bit line extending in a second direction on the first word line, a first memory cell disposed between the first word line and the first bit line, a second word line extending in the first direction on the first bit line, a second bit line extending in the second direction on the second word line, a second memory cell disposed between the second word line and the second bit line, and a first bit line connection structure connected to the first bit line and the second bit line. The first bit line connection structure includes a first bit line contact connected to the first bit line and a second bit line contact, which is connected to the second bit line and vertically overlaps the first bit line contact.Type: ApplicationFiled: September 19, 2018Publication date: May 9, 2019Inventors: JI-HYUN JEONG, Dae-Hwan Kang, Du-Eung Kim, Kwang-Jin Lee
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Patent number: 10263040Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: GrantFiled: February 27, 2018Date of Patent: April 16, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-hyun Jeong, Gwan-hyeob Koh, Dae-hwan Kang
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Patent number: 10249820Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality of first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction.Type: GrantFiled: December 1, 2016Date of Patent: April 2, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang-Woo Lee, Dae-Hwan Kang, Gwan-Hyeob Koh
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Publication number: 20190013466Abstract: A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions.Type: ApplicationFiled: August 23, 2018Publication date: January 10, 2019Inventors: Il-mok PARK, Gwan-hyeob KOH, Dae-hwan KANG
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Publication number: 20180342672Abstract: A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.Type: ApplicationFiled: August 6, 2018Publication date: November 29, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Kyu-Rie SIM, Dae-Hwan Kang, Gwan-Hyeob Koh
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Patent number: 10141502Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. A first conductive line extends in a first direction on a substrate and has a plurality of protrusions and recesses that are alternately formed thereon. A second conductive line is arranged over the first conductive line in a second direction such that the first and the second conductive lines cross at the protrusions. A plurality of memory cell structures is positioned on the protrusions of the first conductive line and is contact with the second conductive line. A thermal insulating plug is positioned on the recesses of the first conductive line and reduces heat transfer between a pair of the neighboring cell structures in the first direction. Accordingly, the heat cross talk is reduced between the neighboring cell structures along the conductive line.Type: GrantFiled: January 27, 2017Date of Patent: November 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Il-Mok Park, Dae-Hwan Kang, Gwan-Hyeob Koh
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Patent number: 10141373Abstract: A plurality of first conductive patterns is disposed on a substrate. Each of the plurality of first conductive patterns extends in a first direction. A first selection pattern is disposed on each of the plurality of first conductive patterns. A first barrier portion surrounds the first selection pattern. A first electrode and a first variable resistance pattern are disposed on the first selection pattern. A plurality of second conductive patterns is disposed on the first variable resistance pattern. Each of the plurality of second conductive patterns extends in a second direction crossing the first direction.Type: GrantFiled: December 22, 2016Date of Patent: November 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Song-Yi Kim, Jae-Kyu Lee, Dae-Hwan Kang, Gwan-Hyeob Koh
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Publication number: 20180247978Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.Type: ApplicationFiled: April 27, 2018Publication date: August 30, 2018Inventors: KYU-RIE SIM, Gwan-Hyeob Koh, Dae-Hwan Kang
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Patent number: 10062840Abstract: A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.Type: GrantFiled: October 24, 2016Date of Patent: August 28, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Rie Sim, Dae-Hwan Kang, Gwan-Hyeob Koh
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Patent number: 10062841Abstract: A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions.Type: GrantFiled: November 29, 2016Date of Patent: August 28, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Il-mok Park, Gwan-hyeob Koh, Dae-hwan Kang
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Publication number: 20180190718Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Inventors: Ji-hyun Jeong, Gwan-hyeob Koh, Dae-hwan Kang
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Patent number: 9991315Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.Type: GrantFiled: June 26, 2017Date of Patent: June 5, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Masayuki Terai, Gwan-hyeob Koh, Dae-hwan Kang
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Publication number: 20180145252Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.Type: ApplicationFiled: January 5, 2018Publication date: May 24, 2018Inventors: JI-HYUN JEONG, JIN-WOO LEE, GWAN-HYEOB KOH, DAE-HWAN KANG
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Patent number: 9941333Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: GrantFiled: October 7, 2016Date of Patent: April 10, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-hyun Jeong, Gwan-hyeob Koh, Dae-hwan Kang
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Patent number: 9887354Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.Type: GrantFiled: October 18, 2016Date of Patent: February 6, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hyun Jeong, Jin-Woo Lee, Gwan-Hyeob Koh, Dae-Hwan Kang
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Publication number: 20170309683Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.Type: ApplicationFiled: June 26, 2017Publication date: October 26, 2017Inventors: KYU-RIE SIM, Gwan-Hyeob Koh, Dae-Hwan Kang
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Publication number: 20170294483Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Inventors: Masayuki TERAI, Gwan-hyeob KOH, Dae-hwan KANG