Patents by Inventor Dae Hyun Park
Dae Hyun Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190341353Abstract: A fan-out semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, an encapsulant encapsulating the semiconductor chip, and an electromagnetic wave shielding layer disposed on the semiconductor chip and including a plurality of degassing holes. The electromagnetic wave shielding layer includes a first region and a second region in which densities of the degassing holes are different from each other, the first region having a density of the degassing holes higher than a density of the degassing holes in the second region.Type: ApplicationFiled: August 20, 2018Publication date: November 7, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mi Ja HAN, Dae Hyun PARK, Seong Hwan LEE, Sang Jong LEE
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Patent number: 10333193Abstract: A printed circuit board and a printed circuit board includes a signal transmitting part; a ground part that includes an impedance adjusting part and a dummy part; and an insulating layer disposed between the signal transmitting part and the ground part.Type: GrantFiled: June 29, 2015Date of Patent: June 25, 2019Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Dae Hyun Park, Han Kim
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Publication number: 20190182950Abstract: A circuit board includes a first conductive layer, a second conductive layer, and a first insulating layer disposed between the first conductive layer and the second conductive layer, wherein the first conductive layer includes a signal line, the second conductive layer includes a ground line, and the ground line of the second conductive layer includes a pattern area patterned in a meander shape.Type: ApplicationFiled: February 4, 2019Publication date: June 13, 2019Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Han KIM, Seong Hee CHOI, Dae Hyun PARK
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Patent number: 10304807Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.Type: GrantFiled: April 12, 2018Date of Patent: May 28, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Hyun Park, Eun Jung Jo, Sung Won Jeong, Han Kim, Mi Ja Han
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Patent number: 10262949Abstract: The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.Type: GrantFiled: April 3, 2018Date of Patent: April 16, 2019Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Dae Hyun Park, Han Kim, Kang Heon Hur, Young Gwan Ko, Jung Ho Shim
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Patent number: 10256200Abstract: An electronic component package and a method of manufacturing the same are provided. The electronic component package includes a frame having a through-hole, an electronic component disposed in the through-hole of the frame, and a redistribution part disposed at one side of the frame and the electronic component. One or more first wiring layers of the frame are electrically connected to the electronic component through the redistribution part.Type: GrantFiled: January 22, 2018Date of Patent: April 9, 2019Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Dae Hyun Park, Han Kim, Kang Heon Hur, Young Gwan Ko, Jung Ho Shim
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Patent number: 10251259Abstract: A circuit board includes a first conductive layer, a second conductive layer, and a first insulating layer disposed between the first conductive layer and the second conductive layer, wherein the first conductive layer includes a signal line, the second conductive layer includes a ground line, and the ground line of the second conductive layer includes a pattern area patterned in a meander shape.Type: GrantFiled: June 30, 2016Date of Patent: April 2, 2019Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Han Kim, Seong Hee Choi, Dae Hyun Park
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Patent number: 10217631Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The first connection member includes a first electromagnetic interference (EMI) blocking part surrounding side surfaces of the semiconductor chip, the second connection member includes a second EMI blocking part surrounding the redistribution layer, and the first EMI blocking part and the second EMI blocking part are connected to each other.Type: GrantFiled: August 9, 2017Date of Patent: February 26, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Han Kim, Mi Ja Han, Dae Hyun Park, Sang Jong Lee, Seong Hee Choi
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Patent number: 10199337Abstract: An electronic component package and a method of manufacturing the same are provided. The electronic component package includes a frame having a through-hole, an electronic component disposed in the through-hole of the frame, and a redistribution part disposed at one side of the frame and the electronic component. One or more first wiring layers of the frame are electrically connected to the electronic component through the redistribution part.Type: GrantFiled: May 2, 2016Date of Patent: February 5, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Hyun Park, Han Kim, Kang Heon Hur, Young Gwan Ko, Jung Ho Shim
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Patent number: 10157886Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.Type: GrantFiled: February 21, 2017Date of Patent: December 18, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Hyun Park, Eun Jung Jo, Sung Won Jeong, Han Kim, Mi Ja Han
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Patent number: 10157851Abstract: The present disclosure relates to a fan-out semiconductor package in which a plurality of semiconductor chips are stacked and packaged, and are disposed in a special form to be thus electrically connected to a redistribution layer of a connection member through vias rather than wires. The fan-out semiconductor package can further include a connection member having a through-hole, and at least one of the semiconductor chips can be disposed in the through-hole.Type: GrantFiled: August 1, 2017Date of Patent: December 18, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Hyung Joon Kim, Jung Ho Shim, Dae Hyun Park, Han Kim
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Patent number: 10121769Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.Type: GrantFiled: February 21, 2017Date of Patent: November 6, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Hyun Park, Eun Jung Jo, Sung Won Jeong, Han Kim, Mi Ja Han
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Publication number: 20180293556Abstract: A blockchain-based method is described which is related to transferring electronic currency from a payer to a payee. In some embodiments, a first process, a second process and a third process are performed. The first process includes receiving a processing request for a target transaction from a terminal of a payer, and transferring the processing request to a first blockchain node among a plurality of blockchain nodes. When a verification result indicates that the target transaction is valid, the method proceeds to performing the second and third processes. The second process includes transferring electronic currency from an electronic wallet of the payer to an electronic wallet of the payee. The third process includes recording data for the target transaction in a new block, and spreading the new block over the blockchain network. In some embodiments, the second process and the third process are performed in parallel.Type: ApplicationFiled: March 30, 2018Publication date: October 11, 2018Applicant: SAMSUNG SDS CO., LTD.Inventors: Nyun Soo HYUN, Sang Hyeon KIM, Jeong Ho KIM, Kyung Jin KIM, Dae Hyun PARK
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Publication number: 20180293576Abstract: Provided are a blockchain-based custom currency transaction system comprising a plurality of blockchain nodes configured to establish a peer-to-peer (P2P)-based blockchain network, distribute and manage blockchain data in which a plurality of blocks are connected in a chain form, and record, using the blockchain data, transaction data of a custom currency defined based on a cryptocurrency and a service providing server configured to interwork with the blockchain network and provide a transaction service for the custom currency, wherein the transaction data comprises first information about a first currency amount of the custom currency to be transacted and second information about a second currency amount of the cryptocurrency to be transacted.Type: ApplicationFiled: March 23, 2018Publication date: October 11, 2018Applicant: SAMSUNG SDS CO., LTD.Inventors: Kwang Woo SONG, Jae Ho KIM, Mun Seok YANG, Dae Hyun PARK
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Patent number: 10083929Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip, and at least one of the first connection member and the second connection member includes a dummy pattern layer.Type: GrantFiled: August 1, 2017Date of Patent: September 25, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seong Hee Choi, Han Kim, Dae Hyun Park, Mi Ja Han
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Publication number: 20180233454Abstract: The present disclosure relates to a fan-out semiconductor package in which a plurality of semiconductor chips are stacked and packaged, and are disposed in a special form to be thus electrically connected to a redistribution layer of a connection member through vias rather than wires. The fan-out semiconductor package can further include a connection member having a through-hole, and at least one of the semiconductor chips can be disposed in the through-hole.Type: ApplicationFiled: April 17, 2018Publication date: August 16, 2018Inventors: Hyung Joon KIM, Jung Ho SHIM, Dae Hyun PARK, Han KIM
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Publication number: 20180233489Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.Type: ApplicationFiled: April 12, 2018Publication date: August 16, 2018Inventors: Dae Hyun PARK, Eun Jung JO, Sung Won JEONG, Han KIM, Mi Ja HAN
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Publication number: 20180226351Abstract: The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.Type: ApplicationFiled: April 3, 2018Publication date: August 9, 2018Inventors: Dae Hyun PARK, Han KIM, Kang Heon HUR, Young Gwan KO, Jung Ho SHIM
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Publication number: 20180174994Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip, and at least one of the first connection member and the second connection member includes a dummy pattern layer.Type: ApplicationFiled: August 1, 2017Publication date: June 21, 2018Inventors: Seong Hee CHOI, Han KIM, Dae Hyun PARK, Mi Ja HAN
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Publication number: 20180174974Abstract: The present disclosure relates to a fan-out semiconductor package in which a plurality of semiconductor chips are stacked and packaged, and are disposed in a special form to be thus electrically connected to a redistribution layer of a connection member through vias rather than wires. The fan-out semiconductor package can further include a connection member having a through-hole, and at least one of the semiconductor chips can be disposed in the through-hole.Type: ApplicationFiled: August 1, 2017Publication date: June 21, 2018Inventors: Hyung Joon KIM, Jung Ho SHIM, Dae Hyun PARK, Han KIM