Abstract: The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.

Abstract: An electronic component package and a method of manufacturing the same are provided. The electronic component package includes a frame having a through-hole, an electronic component disposed in the through-hole of the frame, and a redistribution part disposed at one side of the frame and the electronic component. One or more first wiring layers of the frame are electrically connected to the electronic component through the redistribution part.

Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, first and second semiconductor chips disposed in the through-hole, an encapsulant encapsulating at least portions of the first connection member, the first semiconductor chip, and the second semiconductor chip, and a second connection member disposed on the first connection member and on active surfaces of the first semiconductor chip and the second semiconductor chip. A redistribution layer of the second connection member is respectively connected to both the first and second connection pads through first and second conductors, and the second conductor has a height greater than that of the first conductor.

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The first connection member includes a first electromagnetic interference (EMI) blocking part surrounding side surfaces of the semiconductor chip, the second connection member includes a second EMI blocking part surrounding the redistribution layer, and the first EMI blocking part and the second EMI blocking part are connected to each other.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the first connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip.

Abstract: A circuit board includes a first conductive layer, a second conductive layer, and a first insulating layer disposed between the first conductive layer and the second conductive layer, wherein the first conductive layer includes a signal line, the second conductive layer includes a ground line, and the ground line of the second conductive layer includes a pattern area patterned in a meander shape.

Abstract: The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.

Abstract: A printed circuit board and a method of manufacturing a printed circuit board are provided. The printed circuit board includes a base, a wiring structure disposed on at least one of a surface and an interior of the base, and a plurality of stitching vias penetrating through the base in a thickness direction along an edge of the base and having side surfaces exposed externally.

Abstract: An electronic component package and a method of manufacturing the same are provided. The electronic component package includes a frame having a through-hole, an electronic component disposed in the through-hole of the frame, and a redistribution part disposed at one side of the frame and the electronic component. One or more first wiring layers of the frame are electrically connected to the electronic component through the redistribution part.

Abstract: A printed circuit board includes a signal transmitting part and a ground part disposed having an insulating layer therebetween. The ground part includes an impedance adjusting part.

Abstract: A printed circuit board and a method of manufacturing a printed circuit board are provided. The printed circuit board includes a base, a wiring structure disposed on at least one of a surface and an interior of the base, and a plurality of stitching vias penetrating through the base in a thickness direction along an edge of the base and having side surfaces exposed externally.

Abstract: A substrate having an electronic component embedded therein includes a first insulating layer including a cavity and including first and second circuit patterns provided on upper and lower surfaces thereof, respectively; the electronic component at least partially inserted into the cavity and including an external electrode; a plurality of build-up insulating layers stacked on or beneath the first insulating layer; upper and lower circuit patterns formed on the build-up insulating layers, respectively; and a plurality of vias connecting the external electrode, the upper circuit pattern, the first circuit pattern, the second circuit pattern, and the lower circuit pattern.

Abstract: A printed circuit board and a printed circuit board includes a signal transmitting part; a ground part that includes an impedance adjusting part and a dummy part; and an insulating layer disposed between the signal transmitting part and the ground part.

Abstract: A printed circuit board includes a signal transmitting part and a ground part disposed having an insulating layer therebetween. The ground part includes an impedance adjusting part.

Abstract: A shopping cart tray includes a trapezoidal bottom plate, a front plate, a rear plate, and right and left side plates. The trapezoidal bottom plate is configured to fit in a loading space of a shopping cart. The front plate extends from a front side of the trapezoidal bottom plate. The rear plate extends from a rear side of the trapezoidal bottom plate. The right side plate extends from a right side of the trapezoidal bottom plate. The left side plate extends from a left side of the trapezoidal bottom plate. The shopping cart tray fits into the shopping cart and maximize a usage of the loading space. The dimension of the trapezoidal bottom plate is slightly smaller than a dimension of the loading space of the shopping cart.

Abstract: A shopping cart tray includes a trapezoidal bottom plate, a front plate, a rear plate, and right and left side plates. The trapezoidal bottom plate is configured to fit in a loading space of a shopping cart. The front plate extends from a front side of the trapezoidal bottom plate. The rear plate extends from a rear side of the trapezoidal bottom plate. The right side plate extends from a right side of the trapezoidal bottom plate. The left side plate extends from a left side of the trapezoidal bottom plate. The shopping cart tray fits into the shopping cart and maximize a usage of the loading space. The dimension of the trapezoidal bottom plate is slightly smaller than a dimension of the loading space of the shopping cart.

Abstract: An EMI noise reduction package board, having a top layer and a bottom layer, one of which having a semiconductor device mounted thereon, can include: a first area having a signal layer arranged on one surface thereof; and a second area placed on a lateral side of the first area and having unit structures arranged repeatedly therein, the unit structures configured for inhibiting EMI noise from being radiated to an outside through the lateral side of the first area. The unit structure can include: a top conductive plate and a bottom conductive plate, formed, respectively, on the top layer and the bottom layer of the second area to face each other in a pair; and a via, connecting the top conductive plate with the bottom conductive plate.

Abstract: An electromagnetic bandgap structure and a printed circuit board that solve a mixed signal problem are disclosed. In accordance with embodiments of the present invention, the electromagnetic bandgap structure includes a first metal layer; a first dielectric layer, stacked in the first metal layer; a second metal layer, stacked in the first dielectric layer, and having a holed formed at a position of the second dielectric layer; a second dielectric layer, stacked in the second metal layer; a metal plate, stacked in the second dielectric layer; a first via, penetrating the hole formed in the second metal layer and connecting the first metal layer and the metal plate; a third dielectric layer, stacked in the metal plate and the second dielectric layer; a third metal layer, stacked in the third dielectric layer; and a second via, connecting the second metal layer to the third metal layer.

Abstract: A substrate having an electronic component embedded therein includes a first insulating layer including a cavity and including first and second circuit patterns provided on upper and lower surfaces thereof, respectively; the electronic component at least partially inserted into the cavity and including an external electrode; a plurality of build-up insulating layers stacked on or beneath the first insulating layer; upper and lower circuit patterns formed on the build-up insulating layers, respectively; and a plurality of vias connecting the external electrode, the upper circuit pattern, the first circuit pattern, the second circuit pattern, and the lower circuit pattern.