Patents by Inventor Dae Ik Kim

Dae Ik Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200306266
    Abstract: A solid dispersion of dutasteride for improving the solubility or dissolution rate of poorly soluble dutasteride, a method for preparing the solid dispersion, and a pharmaceutical composition including the solid dispersion are provided. The solid dispersion includes: a coprecipitate including dutasteride and a water-soluble polymeric carrier; and an adsorbent. The dutasteride and the water-soluble polymeric carrier are present in a weight ratio of 1:10-100 in the coprecipitate. The solid dispersion exhibits a dissolution rate equal to or higher than AVODARTĀ® soft capsules and contains a minimal amount of related substances, achieving good storage stability.
    Type: Application
    Filed: November 12, 2018
    Publication date: October 1, 2020
    Inventors: Dae Ik KIM, Woo Cheoul SHIN
  • Patent number: 10332831
    Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Augustin Jinwoo Hong, Dae-Ik Kim, Chan-Sic Yoon, Ki-Seok Lee, Dong-Min Han, Sung-Ho Jang, Yoo-Sang Hwang, Bong-Soo Kim, Je-Min Park
  • Patent number: 10129895
    Abstract: Disclosed are a method and an apparatus that reflect the quantity of wireless resources allocatable to a user terminal in a scheduling target cell to calculate the quantity of available wireless resources for quality of service (QoS) requirements for each kind of varied traffic of user terminals and a metric having a flexible weight for the QoS requirements and support efficient wireless resource scheduling among the user terminals.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: November 13, 2018
    Assignees: Electronics and Telecommunications Research Institute, University-Industry Cooperation Group of Kyung Hee University
    Inventors: Kyung Sook Kim, Een Kee Hong, Dong Seung Kwon, Dae Ik Kim, Sung Kyung Kim, Jee Hyeon Na, Ye Ok Jang, Eun Hyung Cho, Hyun Jin Kim
  • Patent number: 10128252
    Abstract: A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating pattern formed on the substrate and connected to the cell active region, a bit line structure including a thin conductive pattern, contacting a top surface of the direct contact and extending in one direction, and a peripheral gate structure in the peripheral active region. The peripheral gate structure include a stacked structure of a peripheral gate insulating pattern and a peripheral gate conductive pattern, the thin conductive pattern includes a first material and the peripheral gate conductive pattern include the first material, and a level of an upper surface of the thin conductive pattern is lower than a level of an upper surface of the peripheral gate conductive pattern.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-seok Lee, Dae-ik Kim, Yoo-sang Hwang, Bong-soo Kim, Je-min Park
  • Patent number: 10103101
    Abstract: A semiconductor device includes: a first interconnection line and a second interconnection line which extend apart from each other on a first plane at a first level on a substrate; a bypass interconnection line that extends on a second plane at a second level on the substrate; and a plurality of contact plugs for connecting the bypass interconnection line to the first interconnection line and the second interconnection line. A method includes forming a bypass interconnection line spaced apart from a substrate and forming on a same plane a plurality of interconnection lines connected to the bypass interconnection line via a plurality of contact plugs.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: October 16, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-min Park, Dae-ik Kim
  • Patent number: 10057188
    Abstract: A method of providing a multicast service is provided by a terminal in a terminal-to-terminal direct communication. The terminal transmits a service start request message requesting a start of a multicast service to a multicast server, and receives a service start response message including a result of permitting a start request from the multicast server. The terminal receives, via a base station, resource information of a resource which a multicast coordinator allocates to the multicast service in accordance with a request of the multicast server, and transmits multicast service data based on the resource information.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: August 21, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jeehyeon Na, Dae Ik Kim, Hyung-Sub Kim, Yeon Seung Shin
  • Patent number: 10037999
    Abstract: A semiconductor device includes a substrate including an active region, a plurality of conductive line structures separate from the substrate, a plurality of contact plugs between the plurality of conductive line structures, a plurality of landing pads connected to a corresponding contact plug of the plurality of contact plugs, a landing pad insulation pattern between the plurality of landing pads, and a first insulation spacer between the landing pad insulation pattern and first conductive line structures from among the plurality of conductive line structures.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: July 31, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Sung-eui Kim, Hoon Jeong
  • Patent number: 10039062
    Abstract: A method for controlling, by a base station, uplink transmission power of a mobile terminal. The base station receives an available transmission power amount of the mobile terminal from the mobile terminal. The base station determines a target channel quality value corresponding to a current location of the mobile terminal, on the basis of the available transmission power amount. The base station determines a received channel quality value using an uplink data channel received from the mobile terminal. Further, the base station determines a transmit power control (TPC) using a difference between the target channel quality value and the received channel quality value.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: July 31, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Dae Ik Kim, JeeHyeon Na
  • Publication number: 20180175045
    Abstract: A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating pattern formed on the substrate and connected to the cell active region, a bit line structure including a thin conductive pattern, contacting a top surface of the direct contact and extending in one direction, and a peripheral gate structure in the peripheral active region. The peripheral gate structure include a stacked structure of a peripheral gate insulating pattern and a peripheral gate conductive pattern, the thin conductive pattern includes a first material and the peripheral gate conductive pattern include the first material, and a level of an upper surface of the thin conductive pattern is lower than a level of an upper surface of the peripheral gate conductive pattern.
    Type: Application
    Filed: July 11, 2017
    Publication date: June 21, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ki-seok LEE, Dae-ik Kim, Yoo-sang Hwang, Bong-soo Kim, Je-min Park
  • Publication number: 20180158773
    Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.
    Type: Application
    Filed: June 30, 2017
    Publication date: June 7, 2018
    Inventors: AUGUSTIN JINWOO HONG, DAE-IK KIM, CHAN-SIC YOON, Kl-SEOK LEE, DONG-MIN HAN, SUNG-HO JANG, YOO-SANG HWANG, BONG-SOO KIM, JE-MIN PARK
  • Patent number: 9960039
    Abstract: A method of forming a pattern includes forming a first level pattern layer on a feature layer on a substrate. The first level pattern layer includes a plurality of first line patterns and a plurality of first space burying patterns. The first line patterns extend parallel to one another in a first direction and the first space burying patterns extend parallel to one another in the first direction with first line patterns alternately disposed with first space burying patterns A portion of the plurality of first space burying patterns may be removed to form a second direction pattern space extending intermittently or continuously in the first level pattern layer. A second burying layer filling the second direction pattern space may be formed to form a network structure pattern. The feature layer may be etched with the network structure pattern as an etch mask to form a pattern of holes.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: May 1, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Ik Kim, Eun-Jung Kim, Yoo-Sang Hwang, Bong-Soo Kim, Je-Min Park
  • Patent number: 9953981
    Abstract: A method of manufacturing a semiconductor device includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang, Ji-young Kim
  • Publication number: 20170289921
    Abstract: A method for controlling, by a base station, uplink transmission power of a mobile terminal. The base station receives an available transmission power amount of the mobile terminal from the mobile terminal. The base station determines a target channel quality value corresponding to a current location of the mobile terminal, on the basis of the available transmission power amount. The base station determines a received channel quality value using an uplink data channel received from the mobile terminal. Further, the base station determines a transmit power control (TPC) using a difference between the target channel quality value and the received channel quality value.
    Type: Application
    Filed: March 7, 2017
    Publication date: October 5, 2017
    Inventors: Dae Ik KIM, JeeHyeon NA
  • Patent number: 9754944
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes defined in a support layer and are spaced apart from each other in a first direction and a second direction perpendicular to the first direction and the etch control layer surrounding the isolated contact filling portions, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming interconnection patterns by photo-etching the interconnection layer, the isolated contact patterns, and the etch control portion, the interconnection patterns being relatively narrow in the first direction and relatively wide in the second direction.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang
  • Publication number: 20170186613
    Abstract: A method of forming a pattern includes forming a first level pattern layer on a feature layer on a substrate. The first level pattern layer includes a plurality of first line patterns and a plurality of first space burying patterns. The first line patterns extend parallel to one another in a first direction and the first space burying patterns extend parallel to one another in the first direction with first line patterns alternately disposed with first space burying patterns A portion of the plurality of first space burying patterns may be removed to form a second direction pattern space extending intermittently or continuously in the first level pattern layer. A second burying layer filling the second direction pattern space may be formed to form a network structure pattern. The feature layer may be etched with the network structure pattern as an etch mask to form a pattern of holes.
    Type: Application
    Filed: October 12, 2016
    Publication date: June 29, 2017
    Inventors: DAE-IK KIM, EUN-JUNG KIM, YOO-SANG HWANG, BONG-SOO KIM, JE-MIN PARK
  • Patent number: 9635535
    Abstract: Disclosed is a proximity measurement method and apparatus for device-to-device (D2D) communication in a mobile communication system. The proximity measurement method may include determining whether a cell identification (ID) is included in a packet received from a gateway, verifying whether the cell ID matches a pre-stored cell ID when the cell ID is included, extracting, from the packet, Internet Protocol addresses of mobile terminals transmitting and receiving the packet when the cell ID matches the pre-stored cell ID, searching for IP addresses matched to the extracted IP addresses based on a proximity list including IP addresses of mobile terminals performing D2D communication, and registering, when the extracted IP addresses are absent in the proximity list, the extracted IP addresses in the proximity list and measuring proximity between the mobile terminals.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 25, 2017
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jung Mo Moon, Jee Hyeon Na, Dae Ik Kim, Woo Goo Park
  • Patent number: 9634012
    Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: April 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Jin Park, Chan-sic Yoon, Ki-Seok Lee, Hyeon-Ok Jung, Dae-Ik Kim, Bong-Soo Kim, Yong-Kwan Kim, Eun-Jung Kim, Se-Myeong Jang, Min-su Choi, Sung-Hee Han, Yoo-Sang Hwang
  • Patent number: 9613966
    Abstract: A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct contact connecting a first active area of the plurality of active areas with the bit line, an insulating spacer covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate, a contact pad connected with a side wall of a second active area of the plurality of active areas, which neighbors the first active area, a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad, and a buried contact connected with the contact pad and filling the contact hole.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: April 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Sung-eui Kim
  • Patent number: 9601494
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices include an interlayer insulating layer on a semiconductor substrate, contact pads on the semiconductor substrate and penetrating the interlayer insulating layer, a stopping insulating layer on the interlayer insulating layer, storage electrodes on the contact pads, upper supporters between upper parts of the storage electrodes, side supporters between the storage electrodes and the upper supporters, a capacitor dielectric layer on the storage electrodes, the side supporters, and the upper supporters, and a plate electrode on the capacitor dielectric layer.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Eun Kim, Dae-Ik Kim, Seung-Jun Lee, Young-Seung Cho
  • Patent number: 9601420
    Abstract: A semiconductor device includes a stack structure of a conductive line and an insulating capping line extending in a first direction on a substrate, a plurality of contact plugs arranged in a row along the first direction and having sidewall surfaces facing the conductive line with air spaces between the sidewall surfaces and the conductive line, and a support interposed between the insulating capping line and the contact plugs to limit the height of the air spaces. The width of the support varies or the support is present only intermittently in the first direction. In a method of manufacturing the semiconductor devices, a sacrificial spacer is formed on the side of the stack structure, the spacer is recessed, a support layer is formed in the recess, the support layer is etched to form the support, and then the remainder of the spacer is removed to provide the air spaces.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoo-Sang Hwang, Hyun-Woo Chung, Dae-Ik Kim