Patents by Inventor Dae Ik Kim

Dae Ik Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9754944
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes defined in a support layer and are spaced apart from each other in a first direction and a second direction perpendicular to the first direction and the etch control layer surrounding the isolated contact filling portions, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming interconnection patterns by photo-etching the interconnection layer, the isolated contact patterns, and the etch control portion, the interconnection patterns being relatively narrow in the first direction and relatively wide in the second direction.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang
  • Publication number: 20170186613
    Abstract: A method of forming a pattern includes forming a first level pattern layer on a feature layer on a substrate. The first level pattern layer includes a plurality of first line patterns and a plurality of first space burying patterns. The first line patterns extend parallel to one another in a first direction and the first space burying patterns extend parallel to one another in the first direction with first line patterns alternately disposed with first space burying patterns A portion of the plurality of first space burying patterns may be removed to form a second direction pattern space extending intermittently or continuously in the first level pattern layer. A second burying layer filling the second direction pattern space may be formed to form a network structure pattern. The feature layer may be etched with the network structure pattern as an etch mask to form a pattern of holes.
    Type: Application
    Filed: October 12, 2016
    Publication date: June 29, 2017
    Inventors: DAE-IK KIM, EUN-JUNG KIM, YOO-SANG HWANG, BONG-SOO KIM, JE-MIN PARK
  • Patent number: 9635535
    Abstract: Disclosed is a proximity measurement method and apparatus for device-to-device (D2D) communication in a mobile communication system. The proximity measurement method may include determining whether a cell identification (ID) is included in a packet received from a gateway, verifying whether the cell ID matches a pre-stored cell ID when the cell ID is included, extracting, from the packet, Internet Protocol addresses of mobile terminals transmitting and receiving the packet when the cell ID matches the pre-stored cell ID, searching for IP addresses matched to the extracted IP addresses based on a proximity list including IP addresses of mobile terminals performing D2D communication, and registering, when the extracted IP addresses are absent in the proximity list, the extracted IP addresses in the proximity list and measuring proximity between the mobile terminals.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 25, 2017
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jung Mo Moon, Jee Hyeon Na, Dae Ik Kim, Woo Goo Park
  • Patent number: 9634012
    Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: April 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Jin Park, Chan-sic Yoon, Ki-Seok Lee, Hyeon-Ok Jung, Dae-Ik Kim, Bong-Soo Kim, Yong-Kwan Kim, Eun-Jung Kim, Se-Myeong Jang, Min-su Choi, Sung-Hee Han, Yoo-Sang Hwang
  • Patent number: 9613966
    Abstract: A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct contact connecting a first active area of the plurality of active areas with the bit line, an insulating spacer covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate, a contact pad connected with a side wall of a second active area of the plurality of active areas, which neighbors the first active area, a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad, and a buried contact connected with the contact pad and filling the contact hole.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: April 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Sung-eui Kim
  • Patent number: 9601420
    Abstract: A semiconductor device includes a stack structure of a conductive line and an insulating capping line extending in a first direction on a substrate, a plurality of contact plugs arranged in a row along the first direction and having sidewall surfaces facing the conductive line with air spaces between the sidewall surfaces and the conductive line, and a support interposed between the insulating capping line and the contact plugs to limit the height of the air spaces. The width of the support varies or the support is present only intermittently in the first direction. In a method of manufacturing the semiconductor devices, a sacrificial spacer is formed on the side of the stack structure, the spacer is recessed, a support layer is formed in the recess, the support layer is etched to form the support, and then the remainder of the spacer is removed to provide the air spaces.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoo-Sang Hwang, Hyun-Woo Chung, Dae-Ik Kim
  • Patent number: 9601494
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices include an interlayer insulating layer on a semiconductor substrate, contact pads on the semiconductor substrate and penetrating the interlayer insulating layer, a stopping insulating layer on the interlayer insulating layer, storage electrodes on the contact pads, upper supporters between upper parts of the storage electrodes, side supporters between the storage electrodes and the upper supporters, a capacitor dielectric layer on the storage electrodes, the side supporters, and the upper supporters, and a plate electrode on the capacitor dielectric layer.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Eun Kim, Dae-Ik Kim, Seung-Jun Lee, Young-Seung Cho
  • Publication number: 20170062328
    Abstract: A semiconductor device includes: a first interconnection line and a second interconnection line which extend apart from each other on a first plane at a first level on a substrate; a bypass interconnection line that extends on a second plane at a second level on the substrate; and a plurality of contact plugs for connecting the bypass interconnection line to the first interconnection line and the second interconnection line. A method includes forming a bypass interconnection line spaced apart from a substrate and forming on a same plane a plurality of interconnection lines connected to the bypass interconnection line via a plurality of contact plugs.
    Type: Application
    Filed: November 9, 2016
    Publication date: March 2, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Je-min PARK, Dae-ik KIM
  • Patent number: 9570409
    Abstract: A semiconductor device includes: a first interconnection line and a second interconnection line which extend apart from each other on a first plane at a first level on a substrate; a bypass interconnection line that extends on a second plane at a second level on the substrate; and a plurality of contact plugs for connecting the bypass interconnection line to the first interconnection line and the second interconnection line. A method includes forming a bypass interconnection line spaced apart from a substrate and forming on a same plane a plurality of interconnection lines connected to the bypass interconnection line via a plurality of contact plugs.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: February 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-min Park, Dae-ik Kim
  • Patent number: 9570510
    Abstract: An MRAM device may include semiconductor structures, a common source region, a drain region, a channel region, gate structures, word line structures, MTJ structures, and bit line structures arranged on a substrate. Each of the semiconductor structures may include a first semiconductor pattern having a substantially linear shape extending in a first direction that is substantially parallel to a top surface of the substrate, and a plurality of second patterns that each extend in a third direction substantially perpendicular to the top surface of the substrate. A common source region and drain region may be formed in each of the semiconductor structures to be spaced apart from each other in the third direction, and the channel region may be arranged between the common source region and the drain region. Gate structures may be formed between adjacent second semiconductor patterns in the second direction. Word line structures may electrically connect gate structures arranged in the first direction to each other.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: February 14, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Jung Kim, Se-Myeong Jang, Dae-Ik Kim, Je-Min Park, Yoo-Sang Hwang
  • Publication number: 20170025420
    Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.
    Type: Application
    Filed: February 4, 2016
    Publication date: January 26, 2017
    Inventors: Tae-Jin Park, Chan-sic Yoon, Ki-Seok Lee, Hyeon-Ok Jung, Dae-Ik Kim, Bong-Soo Kim, Yong-Kwan Kim, Eun-Jung Kim, Se-Myeong Jang, Min-su Choi, Sung-Hee Han, Yoo-Sang Hwang
  • Patent number: 9548260
    Abstract: Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at least an insulating layer, and a conductive plug structure electrically connecting the conductive line to the target connection region, wherein the conductive plug includes a first conductive plug having a first side wall, a bottom surface contacting the target connection region of the substrate, and a second side wall facing the first side wall of the conductive line, and a second conductive plug between the conductive line and the first conductive plug. The second conductive plug contacts both the first side wall of the conductive line and the second side wall of the first conductive plug.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: January 17, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-min Park, Dae-ik Kim, Ji-young Kim, Nak-jin Son, Yoo-sang Hwang
  • Publication number: 20170006624
    Abstract: Disclosed are a method and an apparatus that reflect the quantity of wireless resources allocatable to a user terminal in a scheduling target cell to calculate the quantity of available wireless resources for quality of service (QoS) requirements for each kind of varied traffic of user terminals and a metric having a flexible weight for the QoS requirements and support efficient wireless resource scheduling among the user terminals.
    Type: Application
    Filed: June 15, 2016
    Publication date: January 5, 2017
    Inventors: Kyung Sook KIM, Een Kee HONG, Dong Seung KWON, Dae Ik KIM, Sung Kyung KIM, Jee Hyeon NA, Ye Ok JANG, Eun Hyung CHO, Hyun Jin KIM
  • Patent number: 9521618
    Abstract: Disclosed is a discovery method and apparatus for device-to-device (D2D) communication in a cellular mobile communication system. The discovery method performed by the discovery apparatus may include obtaining, from a server managing information associated with terminals providing a service using a D2D communication scheme over a mobile communication network, information associated with a service provided by the terminals, selecting a service of interest based on the information associated with the service, receiving, from a base station, information associated with a discovery radio resource allocated to the terminals providing the service of interest, and discovering the terminals providing the service of interest based on the information associated with the discovery radio resource.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: December 13, 2016
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Dae Ik Kim, Jee Hyeon Na, Jung Mo Moon
  • Publication number: 20160322362
    Abstract: A method of manufacturing a semiconductor device includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.
    Type: Application
    Filed: July 12, 2016
    Publication date: November 3, 2016
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang, Ji-young Kim
  • Patent number: 9419000
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: August 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang, Ji-young Kim
  • Patent number: 9398601
    Abstract: Disclosed is a method and apparatus for scheduling in a cellular-based device-to-device (D2D) communication. The method of scheduling a cellular resource used in a base station for a D2D communication between terminals may include grouping, by a proximity coordinator, a cellular resource of an adjacent base station based on cell information of a base station, managing a resource to be allocated to the terminal and a resource allocated previously to the terminal based on the grouped resource, and allocating the grouped resource to the terminal based on information associated with the resource to be allocated and the previously allocated resource when a request for D2D communication between terminals located in different cells is received.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: July 19, 2016
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jee Hyeon Na, Jung Mo Moon, Dae Ik Kim, Sang Ho Lee, Woo Goo Park
  • Patent number: 9374683
    Abstract: Disclosed is a method and an apparatus for device-to-device (D2D) multicast communication in a cellular mobile communication system. The method for D2D communication may include transmitting a server designation request message requesting registration as a server terminal to a base station, and transmitting service information using a D2D multicast or broadcast communication scheme based on a radio resource allocated by the base station.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: June 21, 2016
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Ho Lee, Jee Hyeon Na, Dae Ik Kim, Jung Mo Moon, Woo Goo Park
  • Patent number: 9349633
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation layer on a substrate, where an active pattern is defined, forming an insulating interlayer on the active pattern of the substrate and the isolation layer, removing portions of the insulating interlayer, the active pattern and the isolation layer to form a first recess, forming a first contact in the first recess on a first region of the active pattern exposed by the first recess, removing portions of the active pattern and the isolation layer in the first recess by performing an isotropic etching process, to form an enlarged first recess, and filling the enlarged first recess to form a first spacer that surrounds a sidewall of the first contact.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: May 24, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Ik Kim, Sung-Eui Kim, Hyoung-Sub Kim, Sung-Kwan Choi
  • Publication number: 20160112345
    Abstract: A method of providing a multicast service is provided by a terminal in a terminal-to-terminal direct communication. The terminal transmits a service start request message requesting a start of a multicast service to a multicast server, and receives a service start response message including a result of permitting a start request from the multicast server. The terminal receives, via a base station, resource information of a resource which a multicast coordinator allocates to the multicast service in accordance with a request of the multicast server, and transmits multicast service data based on the resource information.
    Type: Application
    Filed: September 24, 2015
    Publication date: April 21, 2016
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jeehyeon NA, Dae Ik KIM, Hyung-Sub KIM, Yeon Seung SHIN