Patents by Inventor Dae Ik Kim

Dae Ik Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160113019
    Abstract: A second terminal which performs direct communication with a first terminal receives a signal for measuring a radio channel from the first terminal and calculates radio channel quality. Further, the second terminal calculates a data error rate using replay information indicating whether data are received and compensates for the radio channel quality depending on a data error rate. The second terminal reports the compensated radio channel quality to a base station and the base station uses the compensated radio channel quality to allocate resources used in direct communication.
    Type: Application
    Filed: June 2, 2015
    Publication date: April 21, 2016
    Inventors: Dae Ik KIM, JeeHyeon NA, YEON SEUNG SHIN
  • Patent number: 9318494
    Abstract: A method of forming a DRAM can include forming a plurality of transistors arranged in a first direction on a substrate and forming a bit line structure that extends in the first direction, where the bit line structure being electrically coupled to the plurality of transistors at respective locations in the first direction. A plurality of first landing pads an be formed at alternating ones of the respective locations having a first position in a second direction on the substrate. A plurality of second landing pads can be formed at intervening ones of the respective locations between the alternating ones of the respective locations, where the intervening ones of the respective locations having a second position in the second direction on the substrate wherein second position is shifted in the second direction relative to the first position.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Eun Kim, Dae-Ik Kim, Young-Seung Cho
  • Publication number: 20160049460
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices include an interlayer insulating layer on a semiconductor substrate, contact pads on the semiconductor substrate and penetrating the interlayer insulating layer, a stopping insulating layer on the interlayer insulating layer, storage electrodes on the contact pads, upper supporters between upper parts of the storage electrodes, side supporters between the storage electrodes and the upper supporters, a capacitor dielectric layer on the storage electrodes, the side supporters, and the upper supporters, and a plate electrode on the capacitor dielectric layer.
    Type: Application
    Filed: March 3, 2015
    Publication date: February 18, 2016
    Inventors: Kyung-Eun Kim, Dae-Ik Kim, Seung-Jun Lee, Young-Seung Cho
  • Patent number: 9247550
    Abstract: A method and an apparatus perform radio resource allocation. The radio resource allocation method includes receiving channel quality information from a UE, and allocating radio resources on the basis of the received channel quality information and a characteristic of at least one service to be provided to the UE. Accordingly, the radio resource allocation method can assure QoS, and enhance resource-use efficiency.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 26, 2016
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Dae Ik Kim
  • Publication number: 20160020251
    Abstract: An MRAM device may include semiconductor structures, a common source region, a drain region, a channel region, gate structures, word line structures, MTJ structures, and bit line structures arranged on a substrate. Each of the semiconductor structures may include a first semiconductor pattern having a substantially linear shape extending in a first direction that is substantially parallel to a top surface of the substrate, and a plurality of second patterns that each extend in a third direction substantially perpendicular to the top surface of the substrate. A common source region and drain region may be formed in each of the semiconductor structures to be spaced apart from each other in the third direction, and the channel region may be arranged between the common source region and the drain region. Gate structures may be formed between adjacent second semiconductor patterns in the second direction. Word line structures may electrically connect gate structures arranged in the first direction to each other.
    Type: Application
    Filed: May 28, 2015
    Publication date: January 21, 2016
    Inventors: Eun-Jung KIM, Se-Myeong JANG, Dae-Ik KIM, Je-Min PARK, Yoo-Sang HWANG
  • Publication number: 20160020213
    Abstract: A method of forming a DRAM can include forming a plurality of transistors arranged in a first direction on a substrate and forming a bit line structure that extends in the first direction, where the bit line structure being electrically coupled to the plurality of transistors at respective locations in the first direction. A plurality of first landing pads an be formed at alternating ones of the respective locations having a first position in a second direction on the substrate. A plurality of second landing pads can be formed at intervening ones of the respective locations between the alternating ones of the respective locations, where the intervening ones of the respective locations having a second position in the second direction on the substrate wherein second position is shifted in the second direction relative to the first position.
    Type: Application
    Filed: April 22, 2015
    Publication date: January 21, 2016
    Inventors: Kyung-Eun Kim, Dae-Ik Kim, Young-Seung Cho
  • Publication number: 20150380508
    Abstract: A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct contact connecting a first active area of the plurality of active areas with the bit line, an insulating spacer covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate, a contact pad connected with a side wall of a second active area of the plurality of active areas, which neighbors the first active area, a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad, and a buried contact connected with the contact pad and filling the contact hole.
    Type: Application
    Filed: April 28, 2015
    Publication date: December 31, 2015
    Inventors: Dae-ik KIM, Hyoung-sub KIM, Sung-eui KIM
  • Patent number: 9196620
    Abstract: A semiconductor device includes an insulating interlayer over a substrate in a first region, the insulating layer including contact holes exposing a portion of a surface of the substrate, and contact plugs in the contact holes. The contact plugs include a stacked structure of a first barrier metal layer pattern and a first metal layer pattern. The semiconductor device also includes second metal layer patterns directly contacting with the contact plugs and an upper surface of the insulating interlayer. The second metal layer pattern consists is a metal material layer.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: November 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-Min Park, Dae-Ik Kim
  • Patent number: 9159730
    Abstract: A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: October 13, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Ik Kim, Ho-In Ryu, Nak-Jin Son, Yoo-Sang Hwang
  • Publication number: 20150214146
    Abstract: A semiconductor device includes a substrate including an active region, a plurality of conductive line structures separate from the substrate, a plurality of contact plugs between the plurality of conductive line structures, a plurality of landing pads connected to a corresponding contact plug of the plurality of contact plugs, a landing pad insulation pattern between the plurality of landing pads, and a first insulation spacer between the landing pad insulation pattern and first conductive line structures from among the plurality of conductive line structures.
    Type: Application
    Filed: January 7, 2015
    Publication date: July 30, 2015
    Inventors: Dae-ik KIM, Hyoung-sub KIM, Sung-eui KIM, Hoon JEONG
  • Publication number: 20150162335
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation layer on a substrate, where an active pattern is defined, forming an insulating interlayer on the active pattern of the substrate and the isolation layer, removing portions of the insulating interlayer, the active pattern and the isolation layer to form a first recess, forming a first contact in the first recess on a first region of the active pattern exposed by the first recess, removing portions of the active pattern and the isolation layer in the first recess by performing an isotropic etching process, to form an enlarged first recess, and filling the enlarged first recess to form a first spacer that surrounds a sidewall of the first contact.
    Type: Application
    Filed: December 8, 2014
    Publication date: June 11, 2015
    Inventors: Dae-Ik KIM, Sung-Eui KIM, Hyoung-Sub KIM, Sung-Kwan CHOI
  • Publication number: 20150132943
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes defined in a support layer and are spaced apart from each other in a first direction and a second direction perpendicular to the first direction and the etch control layer surrounding the isolated contact filling portions, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming interconnection patterns by photo-etching the interconnection layer, the isolated contact patterns, and the etch control portion, the interconnection patterns being relatively narrow in the first direction and relatively wide in the second direction.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 14, 2015
    Inventors: Dae-ik KIM, Hyoung-sub KIM, Yoo-sang HWANG
  • Publication number: 20150132942
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 14, 2015
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang, Ji-young Kim
  • Patent number: 9012321
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming a sacrificial film as part of a process of forming a semiconductor device. The sacrificial film has a relatively high etch selectivity with respect to other materials of the semiconductor device so as to reduce loss of etching masks and improve the quality of a components (e.g., buried contacts) of the semiconductor device.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang, Nak-jin Son, Ji-young Kim
  • Publication number: 20150102504
    Abstract: A semiconductor device includes: a first interconnection line and a second interconnection line which extend apart from each other on a first plane at a first level on a substrate; a bypass interconnection line that extends on a second plane at a second level on the substrate; and a plurality of contact plugs for connecting the bypass interconnection line to the first interconnection line and the second interconnection line. A method includes forming a bypass interconnection line spaced apart from a substrate and forming on a same plane a plurality of interconnection lines connected to the bypass interconnection line via a plurality of contact plugs.
    Type: Application
    Filed: September 24, 2014
    Publication date: April 16, 2015
    Inventors: Je-min PARK, Dae-ik KIM
  • Publication number: 20150099344
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming a sacrificial film as part of a process of forming a semiconductor device. The sacrificial film has a relatively high etch selectivity with respect to other materials of the semiconductor device so as to reduce loss of etching masks and improve the quality of a components (e.g., buried contacts) of the semiconductor device.
    Type: Application
    Filed: May 21, 2014
    Publication date: April 9, 2015
    Inventors: Dae-ik KIM, Hyoung-sub KIM, Yoo-sang HWANG, Nak-jin SON, Ji-young KIM
  • Patent number: 8957474
    Abstract: A MOS transistor, can include a u-shaped cross-sectional channel region including spaced apart protruding portions separated by a trench and connected to one another by a connecting portion of the channel region at lower ends of the spaced apart protruding portions of the channel region. First and second impurity regions can be located at opposite ends of the -shaped cross-sectional channel region and separated from one another by the trench. A gate electrode can cover at least a planar face of the u-shaped cross-sectional channel region including the spaced apart protruding portions and the connecting portion and exposing the first and second impurity regions.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Ik Kim, Ji-Young Kim, Hyeong-Sun Hong
  • Patent number: 8902814
    Abstract: Provided is a multimedia broadcast and multicast service controlling apparatus and method based on a user location. The multimedia broadcast and multicast service controlling apparatus may receive MCCH information, may periodically update a service list of a mobile terminal based on the received MCCH information, the service list listing services that are providable, may register a service in a pending list when the service is not included in the updated service list and is requested to be provided, and may provide the service registered in the pending list when the mobile terminal reaches a location where the mobile terminal may provide the service registered in the pending list.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: December 2, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Dae Ik Kim, Chul Park, Jee Hyeon Na, Sang Ho Lee
  • Patent number: 8889539
    Abstract: A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-In Ryu, Bong-Su Kim, Dae-Ik Kim, Ho-Jun Lee, Dae-Young Jang, Si-Hyung Lee
  • Patent number: 8878299
    Abstract: A semiconductor device may include a plurality of memory cells. The memory cells may be formed with respective fin shaped active regions with respective recesses formed therein. Thicknesses of the fins may be made relatively thicker around the recesses, such as by selective epitaxial growth around the recesses. The additional thicknesses may be asymmetrical so that portions of the fin on one side are larger than an opposite side. Related methods and systems are also disclosed.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Seok Lee, Dae-Ik Kim