Patents by Inventor Dae Kwon

Dae Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190280374
    Abstract: An antenna module includes a first connection member including at least one first wiring layer and at least one first insulating layer; an antenna package disposed on a first surface of the first connection member, and including a plurality of antenna members and a plurality of feed vias; an integrated circuit (IC) disposed on a second surface of the first connection member and electrically connected to the corresponding wire of at least one first wiring layer; and a second connection member including at least one second wiring layer electrically connected to the IC and at least one second insulating layer, and disposed between the first connection member and the IC, wherein the second connection member has a third surface facing the first connection member and having an area smaller than that of the second surface, and a fourth surface facing the IC.
    Type: Application
    Filed: August 24, 2018
    Publication date: September 12, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Il KIM, Dae Kwon JUNG, Young Sik HUR, Won Wook SO, Yong Ho BAEK, Woo Jung CHOI
  • Patent number: 10334472
    Abstract: Quality of Service (QoS) switching method and apparatus in a mobile communication system are provided. The method includes determining, based on a total resource usage for providing a plurality of QoSs, the QoS switching relating to level adjustment of the plurality of QoSs corresponding to one of downgrade, upgrade, and grade maintenance, and adjusting levels of the plurality of QoSs according to the determined QoS switching.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Dae-Kwon Jung, Hee-Won Kang, Eun-Jung Kim, Myung-Kwang Byun, Jeong-Ho Lee, Eun-Ho Choi
  • Publication number: 20190083563
    Abstract: The present invention relates to an anti-influenza virus composition containing a Poncirus trifoliata extract as an active ingredient. The composition of the present invention inhibits influenza virus replication and infection, thereby exhibiting excellent effects in the prevention and treatment of influenza virus infection. The present invention provides a composition for preventing, treating, or alleviating diseases caused by influenza virus.
    Type: Application
    Filed: November 23, 2018
    Publication date: March 21, 2019
    Inventors: Young Bong KIM, Kang Chang KIM, Hee Jung LEE, Jong Kwang YOON, Yong Dae KWON, Jae Hyeok HEO, Yoon Ki HEO
  • Publication number: 20190064615
    Abstract: A display device is provided. The display device includes a first substrate including a thin film transistor array and a ground pad disposed on a first surface of the first substrate, a second substrate that faces the first surface of the first substrate and is bonded to the first substrate, a reinforcing substrate that faces a second surface of the first substrate, an antistatic layer disposed between the first substrate and the reinforcing substrate, and a ground path unit formed in a line shape enclosing a side of the first substrate and configured to interconnect the ground pad and the antistatic layer.
    Type: Application
    Filed: August 29, 2018
    Publication date: February 28, 2019
    Applicant: LG DISPLAY CO., LTD.
    Inventors: Changtaek LIM, Jehong PARK, Chiwoong KIM, Yunsung JANG, Sanguk KIM, Dae-Kwon JANG
  • Patent number: 10216082
    Abstract: According to example embodiments of inventive concepts, a layout design system includes a processor, a storage unit configured to store a layout design, and a stitch module. The layout design includes a first pattern group and a second pattern group disposed in accordance with a design. The first pattern group including a first pattern for patterning at a first time. The second pattern group including a second pattern for patterning at a second time that is different than the first time. The stitch module is configured to detect an iso-pattern of the second pattern using the processor. The stitch module is configured to repetitively designate at least one of the first pattern, which is spaced apart from the iso-pattern by a pitch or more, to the second pattern group using the processor.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: February 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-kwon Kang, Ji-Young Jung, Dong-Gyun Kim, Jae-Seok Yang, Sung-Keun Park, Young-Gook Park
  • Patent number: 10153235
    Abstract: The present disclosure relates to an image sensor device including: a fan-out semiconductor package including a first semiconductor chip having an active surface on which a connection pad is disposed, a first connection member disposed on the active surface and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, and a sealing material disposed on the first connection member and sealing at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the first connection member and electrically connected to the first connection member; and a third semiconductor chip disposed on the second semiconductor chip and electrically connected to the second semiconductor chip, in which at least one of the second semiconductor chip or the third semiconductor chip may be an image sensor. The present disclosure also relates to an image sensor module including the image sensor device.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Kwon Jung, Bang Chul Ko, Chul Choi, Jung Hyun Cho, Joo Hwan Jung, Yong Ho Baek, Seung Eun Lee
  • Publication number: 20180231418
    Abstract: The present disclosure relates to a substrate with multiple nano-gaps and a manufacturing method therefor, and more particularly to a multiple nano-gaps substrate with high absorption and capable of using light sources in a wide range, and a manufacturing method therefor.
    Type: Application
    Filed: September 24, 2015
    Publication date: August 16, 2018
    Applicant: Korea Institute of Machinery & Materials
    Inventors: Sung Gyu PARK, Jung-Heum YUN, Dong Ho KIM, Byung Jin CHO, Jung Dae KWON, Chae Won MUN
  • Publication number: 20180130750
    Abstract: The present disclosure relates to an image sensor device including: a fan-out semiconductor package including a first semiconductor chip having an active surface on which a connection pad is disposed, a first connection member disposed on the active surface and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, and a sealing material disposed on the first connection member and sealing at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the first connection member and electrically connected to the first connection member; and a third semiconductor chip disposed on the second semiconductor chip and electrically connected to the second semiconductor chip, in which at least one of the second semiconductor chip or the third semiconductor chip may be an image sensor. The present disclosure also relates to an image sensor module including the image sensor device.
    Type: Application
    Filed: August 21, 2017
    Publication date: May 10, 2018
    Inventors: Dae Kwon JUNG, Bang Chul KO, Chul CHOI, Jung Hyun CHO, Joo Hwan JUNG, Yong Ho BAEK, Seung Eun LEE
  • Patent number: 9928330
    Abstract: In a method of decomposing a layout of a semiconductor device, a polygon, which includes a plurality of intersections at each of which at least two lines are crossed, among polygons included in the layout of the semiconductor device may be determined as a complex polygon. A first stitch may be inserted between the plurality of intersections on the complex polygon. A plurality of decomposed patterns may be generated by performing a pattern dividing operation on the layout.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: March 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Kwon Kang, Ji-young Jung, Dong-Gyun Kim, Jae-Seok Yang, Sung-Wook Hwang
  • Patent number: 9874810
    Abstract: A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: January 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Young Jung, Dae-Kwon Kang, Dong-Gyun Kim, Jae-Seok Yang, Sung-Wook Hwang
  • Publication number: 20180008659
    Abstract: The present invention relates to an anti-influenza virus composition containing a Poncirus trifoliata extract as an active ingredient. The composition of the present invention inhibits influenza virus replication and infection, thereby exhibiting excellent effects in the prevention and treatment of influenza virus infection. The present invention provides a composition for preventing, treating, or alleviating diseases caused by influenza virus.
    Type: Application
    Filed: March 19, 2015
    Publication date: January 11, 2018
    Applicants: Konkuk University Industrial Cooperation Corp., KR Biotech Co., Ltd.
    Inventors: Young Bong KIM, Kang Chang KIM, Hee Jung LEE, Jong Kwang YOON, Yong Dae KWON, Jae Hyeok HEO, Yoon Ki HEO
  • Patent number: 9841672
    Abstract: A method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process includes dividing the layout of the semiconductor device into a first temporary pattern, which includes rectangular features having a rectangular shape, and a second temporary pattern, which includes cross couple features having a Z-shape, generating a third temporary pattern and a fourth temporary pattern by performing a pattern dividing operation on the first temporary pattern in a first direction, generating a first target pattern and a second target pattern by incorporating each of the cross couple features included in the second temporary pattern into one of the third temporary pattern and the fourth temporary pattern, and generating first through fourth decomposed patterns by performing the pattern dividing operation on the first target pattern and the second target pattern in a second direction.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: December 12, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Kwon Kang, Jae-Seok Yang, Sung-Wook Hwang, Dong-Gyun Kim, Ji-Young Jung
  • Patent number: 9836565
    Abstract: Provided are an electronic design automation apparatus and method. The electronic design automation method includes: loading, by a processor, a rule file having limitations on a reference design file; extracting, by the processor, a plurality of unit operations for respectively performing the limitations from the loaded file; and automatically forming, by the processor, a flowchart corresponding to the rule file based on relations between the plurality of unit operations.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: December 5, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Dae-Kwon Kang
  • Publication number: 20170320435
    Abstract: A WiFi wireless rear view parking system comprises a main body, a camera sensor, a Wifi transmission module, a mobile personal electronic device, and a switch. The main body is installed at a license plate of an automobile. The camera sensor is provided in the main body for sensing images and video of rear regions of the automobile and generating images and video data. The Wifi transmission module transmits the image and video data from the camera. The mobile personal electronic device is for receiving image and video data transmitted by the Wifi transmission module and displaying them. The switch is provided in the display device or the mobile personal electronic device and configured for switching orientation of a view by flipping reverse and non-reverse, wherein the view is displayed on the mobile personal electronic device. The WiFi wireless rear view parking system provides rear view of the automobile to a driver. The mobile personal electronic device includes a smartphone.
    Type: Application
    Filed: July 24, 2017
    Publication date: November 9, 2017
    Inventor: Dae Kwon CHUNG
  • Patent number: 9725789
    Abstract: Provided are an apparatus for manufacturing a compound powder, a method of manufacturing an iron-boron compound powder by using the apparatus, a boron alloy powder mixture, a method of manufacturing the boron alloy powder mixture, a combined powder structure, a method of manufacturing the combined powder structure, a steel pipe, and a method of manufacturing the steel pipe The method of manufacturing the boron alloy powder mixture includes: preparing a mixed powder including a boron iron alloy powder and a target powder; heat-treating the mixed powder to boronize at least a portion of the target powder and de-boronize at least a portion of the boron iron alloy powder, thereby de-boronizing the boron iron alloy powder to reduce the melting point of the boron iron alloy powder.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: August 8, 2017
    Assignee: KMT CO., LTD.
    Inventors: Kee-Seok Nam, Jung-Dae Kwon, Jong-Joo Rha, Hee-Chan Ahn, Tae-Su Lim
  • Patent number: 9652578
    Abstract: A layout design method may include receiving predetermined values related to first to third normal fin designs extending in a first direction and arranged in parallel in a second direction perpendicular to the first direction, generating dummy fin designs based on the predetermined values, generating mandrel candidate designs based on the first to third normal fin designs and the dummy fin designs, decomposing the mandrel candidate designs to first and second mandrel mask designs, and generating a final mandrel mask design using one of the first and second mandrel mask designs that satisfies a predetermined condition. A first interval distance in the second direction between the first normal fin design and the second normal fin design may be different from a second interval distance in the second direction between the second normal fin design and the third normal fin design.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: May 16, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Gyun Kim, Sung-Wook Hwang, Dae-Kwon Kang, Jae-Seok Yang, Ji-Young Jung
  • Patent number: 9512751
    Abstract: A device for reducing fuel dilution of a diesel engine may include an engine oil level sensor mounted to an oil pan for storing engine oil, to sense a level of the engine oil, a heater switch switched on by a signal of a controller, when the level of the engine oil in the oil pan is increased to a reference level or more by fuel diluted in the engine oil, and a heater connected to the heater switch in the oil pan, to evaporate the fuel diluted in the engine oil while being operated by an on state of the heater switch.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: December 6, 2016
    Assignee: Hyundai Motor Company
    Inventors: Won Jin Jo, Jae Deuk Lee, Je Rok Chun, Dae Kwon Kim, Young Jic Kim, Jung Hwan Ham, Jin Seok Chang
  • Publication number: 20160313638
    Abstract: A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 27, 2016
    Inventors: Ji-Young Jung, Dae-Kwon KANG, Dong-Gyun KIM, Jae-Seok YANG, Sung-Wook HWANG
  • Publication number: 20160306914
    Abstract: According to example embodiments of inventive concepts, a layout design system includes a processor, a storage unit configured to store a layout design, and a stitch module. The layout design includes a first pattern group and a second pattern group disposed in accordance with a design. The first pattern group including a first pattern for patterning at a first time. The second pattern group including a second pattern for patterning at a second time that is different than the first time. The stitch module is configured to detect an iso-pattern of the second pattern using the processor. The stitch module is configured to repetitively designate at least one of the first pattern, which is spaced apart from the iso-pattern by a pitch or more, to the second pattern group using the processor.
    Type: Application
    Filed: January 20, 2016
    Publication date: October 20, 2016
    Inventors: Dae-kwon KANG, Ji-Young JUNG, Dong-Gyun KIM, Jae-Seok YANG, Sung-Keun PARK, Young-Gook PARK
  • Publication number: 20160188773
    Abstract: Provided are an electronic design automation apparatus and method. The electronic design automation method includes: loading, by a processor, a rule file having limitations on a reference design file; extracting, by the processor, a plurality of unit operations for respectively performing the limitations from the loaded file; and automatically forming, by the processor, a flowchart corresponding to the rule file based on relations between the plurality of unit operations.
    Type: Application
    Filed: August 12, 2015
    Publication date: June 30, 2016
    Inventor: DAE-KWON KANG