Patents by Inventor Dae Sung EOM

Dae Sung EOM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210166791
    Abstract: An apparatus for constructing a library for deriving a material composition using empirical result, which enables acceleration of research on the material-properties relationship. By applying the empirical results of the material composition, missing data of the material compositions can be statistically calculated by using supervised non-linear imputation techniques. The completed composition information of the materials is passed as an input of machine learning material-properties relationship prediction.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 3, 2021
    Inventors: Seung Bum HONG, Eun Ae CHO, Jong Min YUK, Hye Ryung BYON, Yong Soo YANG, Pyuck Pa CHOI, Jong Hwa SHIN, Hyuck Mo LEE, CHI HAO LIOW, Seong Woo CHO, Gun PARK, Yong Ju LEE, Yoon Su SHIM, Moo Ny NA, Ho Sun JUN, Ki Hoon BANG, Myung Joon KIM, Chae Hwa JEONG, Seung Gu KIM, Chung Ik OH, Hong Jun KIM, Jae Gyu KIM, Ji Min OH, Ji Won YEOM, Seong Mun EOM, Hyoung Kyu KIM, Young Joon HAN, Dae Hee LEE, Ho Jun LEE, Jae Woon KIM, Jae Wook SHIN, Hyeon Muk KANG, Jae Yeol PARK, Han Beom JEONG, Jae Sang LEE, Joon Ha CHANG, Yo Han KIM, Su Jung KIM, Hyun Jeong OH, Arthur Baucour, Jae Wook HAN, Kyu Seon JANG, Hye Sung JO, Bo Ryung YOO, Hyeon Jin PARK, Min Gwan CHO, Jun Hyung PARK, Yea Eun KIM, Seok Hwan MIN, Jung Woo CHOI, Young Tae PARK, Doo Sun HONG
  • Patent number: 10985112
    Abstract: A vertical memory device includes: a substrate including a memory cell region and a contact region; a plurality of gate electrodes that extend from the memory cell region to the contact region and include pad portions which are end portions stacked in a step shape in the contact region; a plurality of contact plugs coupled to the pad portions of the gate electrodes; and a plurality of supporters formed below the pad portions of the gate electrodes.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: April 20, 2021
    Assignee: SK hynix Inc.
    Inventor: Dae-Sung Eom
  • Publication number: 20210020658
    Abstract: A semiconductor device includes conductive patterns stacked and spaced apart from each other in a first direction to form a stepped structure, a stepped insulating layer overlapping the stepped structure, contact plugs extending through the stepped insulating layer in the first direction to contact respective contact portions of the conductive patterns, and barrier patterns disposed on sidewalls of the stepped insulating layer.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 21, 2021
    Applicant: SK hynix Inc.
    Inventor: Dae Sung EOM
  • Patent number: 10818690
    Abstract: A semiconductor device includes conductive patterns stacked and spaced apart from each other in a first direction to form a stepped structure, a stepped insulating layer overlapping the stepped structure, contact plugs extending through the stepped insulating layer in the first direction to contact respective contact portions of the conductive patterns, and barrier patterns disposed on sidewalls of the stepped insulating layer.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 27, 2020
    Assignee: SK hynix Inc.
    Inventor: Dae Sung Eom
  • Publication number: 20200152585
    Abstract: A vertical memory device includes: a substrate including a memory cell region and a contact region; a plurality of gate electrodes that extend from the memory cell region to the contact region and include pad portions which are end portions stacked in a step shape in the contact region; a plurality of contact plugs coupled to the pad portions of the gate electrodes; and a plurality of supporters formed below the pad portions of the gate electrodes.
    Type: Application
    Filed: July 2, 2019
    Publication date: May 14, 2020
    Applicant: SK hynix Inc.
    Inventor: Dae-Sung EOM
  • Publication number: 20200144391
    Abstract: A semiconductor device includes a first conductive pattern having a first line portion extending in a first direction and a first bending portion that extends from the first line portion. A closed area, surrounded by the first line portion and the first bending portion, is defined at one side of the first line portion. The semiconductor device further includes a second conductive pattern disposed in the closed area, the second conductive pattern being spaced apart from the first conductive pattern.
    Type: Application
    Filed: June 12, 2019
    Publication date: May 7, 2020
    Applicant: SK hynix Inc.
    Inventor: Dae Sung EOM
  • Patent number: 10559330
    Abstract: A memory device may include a first half memory block, a second half memory block, a row decoder group, and a read/write circuit which may be disposed between the first half memory block and the second half memory block. The read/write circuit may be coupled to the first half memory block and the second half memory block through a first bit line and a second bit line. The row decoder group may be configured to simultaneously select the first half memory block and the second half memory block in response to a single block selection signal.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventor: Dae Sung Eom
  • Publication number: 20200027896
    Abstract: A semiconductor device includes conductive patterns stacked and spaced apart from each other in a first direction to form a stepped structure, a stepped insulating layer overlapping the stepped structure, contact plugs extending through the stepped insulating layer in the first direction to contact respective contact portions of the conductive patterns, and barrier patterns disposed on sidewalls of the stepped insulating layer.
    Type: Application
    Filed: February 26, 2019
    Publication date: January 23, 2020
    Applicant: SK hynix Inc.
    Inventor: Dae Sung EOM
  • Patent number: 10396168
    Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes a pipe gate stack structure in which a portion of a first channel layer is buried. The semiconductor device includes the pipe gate stack structure in which a portion of a second channel layer is buried. The semiconductor device configured to individually control the first and second channel layers.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: August 27, 2019
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Eom, Jeong Sang Kang
  • Publication number: 20190147918
    Abstract: A memory device may include a first half memory block, a second half memory block, a row decoder group, and a read/write circuit which may be disposed between the first half memory block and the second half memory block. The read/write circuit may be coupled to the first half memory block and the second half memory block through a first bit line and a second bit line. The row decoder group may be configured to simultaneously select the first half memory block and the second half memory block in response to a single block selection signal.
    Type: Application
    Filed: June 14, 2018
    Publication date: May 16, 2019
    Applicant: SK hynix Inc.
    Inventor: Dae Sung EOM
  • Publication number: 20190148505
    Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes a pipe gate stack structure in which a portion of a first channel layer is buried. The semiconductor device includes the pipe gate stack structure in which a portion of a second channel layer is buried. The semiconductor device configured to individually control the first and second channel layers.
    Type: Application
    Filed: June 15, 2018
    Publication date: May 16, 2019
    Applicant: SK hynix Inc.
    Inventors: Dae Sung EOM, Jeong Sang KANG
  • Patent number: 10170496
    Abstract: A semiconductor device in accordance with an embodiment may include a cell structure, a source coupling structure, and a source discharge transistor. The cell structure may include alternately stacked first conductive patterns and first interlayer insulating layers enclosing a channel layer. The source coupling structure separated from the cell structure may include alternately stacked second conductive patterns and second interlayer insulating layers. The source discharge transistor may be coupled to the source coupling structure.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: January 1, 2019
    Assignee: SK hynix Inc.
    Inventor: Dae Sung Eom
  • Patent number: 10074664
    Abstract: Disclosed is a semiconductor memory device, including: a slimming structure extended from a cell structure in a direction parallel to the semiconductor substrate, the cell structure having a plurality of cell transistors stacked over a semiconductor substrate; vertical insulating materials extended in a direction crossing the semiconductor substrate and configured to divide the cell structure and the slimming structure into a plurality of memory blocks; contact plugs passing through the vertical insulating materials, respectively, within an area in which the slimming structure is formed; and junctions formed within the semiconductor substrate under the vertical insulating materials, in which the junctions are coupled to the contact plugs, respectively.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventor: Dae Sung Eom
  • Publication number: 20180040629
    Abstract: A semiconductor device in accordance with an embodiment may include a cell structure, a source coupling structure, and a source discharge transistor. The cell structure may include alternately stacked first conductive patterns and first interlayer insulating layers enclosing a channel layer. The source coupling structure separated from the cell structure may include alternately stacked second conductive patterns and second interlayer insulating layers. The source discharge transistor may be coupled to the source coupling structure.
    Type: Application
    Filed: April 13, 2017
    Publication date: February 8, 2018
    Applicant: SK hynix Inc.
    Inventor: Dae Sung EOM
  • Patent number: 9837419
    Abstract: A semiconductor device includes a first memory block and a second memory block in a cell region and a first transistor and a second transistor, respectively corresponding to the first and second memory blocks, in a pass transistor region located below the cell region, wherein each of the first and second transistors includes: a first gate electrode coupled to the first memory block and a second gate electrode coupled to the second memory block.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: December 5, 2017
    Assignee: SK Hynix Inc.
    Inventors: Sung Lae Oh, Dae Sung Eom
  • Patent number: 9761579
    Abstract: A resistor includes a first conductive layer; a second conductive layer protruding from the first conductive layer; a third conductive layer located above and facing the first conductive layer to face the first conductive layer; and at least two contact plugs electrically coupled to the third conductive layer.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 12, 2017
    Assignee: SK hynix Inc.
    Inventor: Dae Sung Eom
  • Patent number: 9761602
    Abstract: A semiconductor memory device to which a Peri Under Cell (PUC) structure is applied is disclosed. The semiconductor memory device includes a word line multilayered structure formed in a cell region, and extending from across the cell region; and a slimming region including a step-shaped pad structure in the word line multilayered structure.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: September 12, 2017
    Assignee: SK Hynix Inc.
    Inventors: Sung Lae Oh, Dae Sung Eom
  • Patent number: 9524975
    Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device may include a dummy structure formed on a peripheral region of a substrate, and insulating spacers configured to pass through the dummy structure and protrude from an upper surface of the dummy structure. The semiconductor device may include first contact plugs configured to pass through the insulating spacers and protrude from upper surfaces of the insulating spacers.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: December 20, 2016
    Assignee: SK hynix Inc.
    Inventor: Dae Sung Eom
  • Patent number: 9520409
    Abstract: A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: December 13, 2016
    Assignee: SK HYNIX INC.
    Inventors: Tae Kyung Kim, Dae Sung Eom
  • Publication number: 20160351672
    Abstract: Disclosed is a semiconductor memory device, including: a slimming structure extended from a cell structure in a direction parallel to the semiconductor substrate, the cell structure having a plurality of cell transistors stacked over a semiconductor substrate; vertical insulating materials extended in a direction crossing the semiconductor substrate and configured to divide the cell structure and the slimming structure into a plurality of memory blocks; contact plugs passing through the vertical insulating materials, respectively, within an area in which the slimming structure is formed; and Junctions formed within the semiconductor substrate under the vertical insulating materials, in which the junctions are coupled to the contact plugs, respectively.
    Type: Application
    Filed: October 9, 2015
    Publication date: December 1, 2016
    Inventor: Dae Sung EOM