Patents by Inventor Dae Sung EOM
Dae Sung EOM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923406Abstract: A semiconductor device includes: a first insulating layer, a plurality of first electrodes penetrating the first insulating layer, a plurality of second electrodes penetrating the first insulating layer, the plurality of second electrodes being located between the plurality of first electrodes: a first high dielectric constant layer having a dielectric constant higher than a dielectric constant of the first insulating layer, a plurality of third electrodes penetrating the first high dielectric constant layer, the plurality of third electrodes being respectively connected to the plurality of first electrodes, and a plurality of fourth electrodes penetrating the first high dielectric constant layer, the plurality of fourth electrodes being located between the plurality of third electrodes.Type: GrantFiled: September 3, 2021Date of Patent: March 5, 2024Assignee: SK hynix Inc.Inventor: Dae Sung Eom
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Publication number: 20240015966Abstract: A semiconductor memory device includes a gate stack structure including a plurality of conductive layers stacked to be spaced apart from each other in a first direction, the gate stack structure surrounding the periphery of a polygonal opening. The semiconductor memory device also includes a stepped structure formed along a sidewall of the polygonal opening.Type: ApplicationFiled: December 14, 2022Publication date: January 11, 2024Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Publication number: 20240008272Abstract: A semiconductor device includes: a stacked structure comprising a plurality of dielectric layers and a plurality of conductive layers, wherein the dielectric layers are alternately stacked with the conductive layers; a groove formed for each conductive layer by recessing the conductive layer to the inside of the stacked structure; and an isolation structure formed through the stacked structure so as to isolate the stacked structure into a first block and a second block. The isolation structure comprises a first isolation structure and a second isolation structure adjacent to the first isolation structure with a gap provided between the first and second isolation structures, and one end of the first isolation structure and the other end of the second isolation structure, which face each other, have a vortex shape when viewed from above.Type: ApplicationFiled: September 15, 2023Publication date: January 4, 2024Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Patent number: 11765895Abstract: A semiconductor device includes: a stacked structure comprising a plurality of dielectric layers and a plurality of conductive layers, wherein the dielectric layers are alternately stacked with the conductive layers; a groove formed for each conductive layer by recessing the conductive layer to the inside of the stacked structure; and an isolation structure formed through the stacked structure so as to isolate the stacked structure into a first block and a second block. The isolation structure comprises a first isolation structure and a second isolation structure adjacent to the first isolation structure with a gap provided between the first and second isolation structures, and one end of the first isolation structure and the other end of the second isolation structure, which face each other, have a vortex shape when viewed from above.Type: GrantFiled: July 28, 2022Date of Patent: September 19, 2023Assignee: SK hynix Inc.Inventor: Dae Sung Eom
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Publication number: 20230217651Abstract: A semiconductor memory device includes: a semiconductor substrate including a first region and a second region; a memory cell array over the first region of the semiconductor substrate; a dummy stack structure over the second region of the semiconductor substrate; a chip guard structure penetrating the dummy stack structure; and a void-containing structure penetrating the dummy stack structure.Type: ApplicationFiled: June 9, 2022Publication date: July 6, 2023Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Publication number: 20220367502Abstract: A semiconductor device includes: a stacked structure comprising a plurality of dielectric layers and a plurality of conductive layers, wherein the dielectric layers are alternately stacked with the conductive layers; a groove formed for each conductive layer by recessing the conductive layer to the inside of the stacked structure; and an isolation structure formed through the stacked structure so as to isolate the stacked structure into a first block and a second block. The isolation structure comprises a first isolation structure and a second isolation structure adjacent to the first isolation structure with a gap provided between the first and second isolation structures, and one end of the first isolation structure and the other end of the second isolation structure, which face each other, have a vortex shape when viewed from above.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Publication number: 20220302248Abstract: A semiconductor device includes: a first insulating layer, a plurality of first electrodes penetrating the first insulating layer, a plurality of second electrodes penetrating the first insulating layer, the plurality of second electrodes being located between the plurality of first electrodes: a first high dielectric constant layer having a dielectric constant higher than a dielectric constant of the first insulating layer, a plurality of third electrodes penetrating the first high dielectric constant layer, the plurality of third electrodes being respectively connected to the plurality of first electrodes, and a plurality of fourth electrodes penetrating the first high dielectric constant layer, the plurality of fourth electrodes being located between the plurality of third electrodes.Type: ApplicationFiled: September 3, 2021Publication date: September 22, 2022Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Patent number: 11404428Abstract: A semiconductor device includes: a stacked structure comprising a plurality of dielectric layers and a plurality of conductive layers, wherein the dielectric layers are alternately stacked with the conductive layers; a groove formed for each conductive layer by recessing the conductive layer to the inside of the stacked structure; and an isolation structure formed through the stacked structure so as to isolate the stacked structure into a first block and a second block. The isolation structure comprises a first isolation structure and a second isolation structure adjacent to the first isolation structure with a gap provided between the first and second isolation structures, and one end of the first isolation structure and the other end of the second isolation structure, which face each other, have a vortex shape when viewed from above.Type: GrantFiled: July 2, 2020Date of Patent: August 2, 2022Assignee: SK hynix Inc.Inventor: Dae Sung Eom
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Publication number: 20220173029Abstract: A semiconductor device includes a first conductive pattern having a first line portion extending in a first direction and a first bending portion that extends from the first line portion. A closed area, surrounded by the first line portion and the first bending portion, is defined at one side of the first line portion. The semiconductor device further includes a second conductive pattern disposed in the closed area, the second conductive pattern being spaced apart from the first conductive pattern.Type: ApplicationFiled: February 16, 2022Publication date: June 2, 2022Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Patent number: 11289420Abstract: A semiconductor device includes a first conductive pattern having a first line portion extending in a first direction and a first bending portion that extends from the first line portion. A closed area, surrounded by the first line portion and the first bending portion, is defined at one side of the first line portion. The semiconductor device further includes a second conductive pattern disposed in the closed area, the second conductive pattern being spaced apart from the first conductive pattern.Type: GrantFiled: June 12, 2019Date of Patent: March 29, 2022Assignee: SK hynix Inc.Inventor: Dae Sung Eom
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Patent number: 11201170Abstract: A semiconductor device includes conductive patterns stacked and spaced apart from each other in a first direction to form a stepped structure, a stepped insulating layer overlapping the stepped structure, contact plugs extending through the stepped insulating layer in the first direction to contact respective contact portions of the conductive patterns, and barrier patterns disposed on sidewalls of the stepped insulating layer.Type: GrantFiled: September 24, 2020Date of Patent: December 14, 2021Assignee: SK hynix Inc.Inventor: Dae Sung Eom
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Publication number: 20210249432Abstract: A semiconductor device includes: a stacked structure comprising a plurality of dielectric layers and a plurality of conductive layers, wherein the dielectric layers are alternately stacked with the conductive layers; a groove formed for each conductive layer by recessing the conductive layer to the inside of the stacked structure; and an isolation structure formed through the stacked structure so as to isolate the stacked structure into a first block and a second block. The isolation structure comprises a first isolation structure and a second isolation structure adjacent to the first isolation structure with a gap provided between the first and second isolation structures, and one end of the first isolation structure and the other end of the second isolation structure, which face each other, have a vortex shape when viewed from above.Type: ApplicationFiled: July 2, 2020Publication date: August 12, 2021Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Patent number: 10985112Abstract: A vertical memory device includes: a substrate including a memory cell region and a contact region; a plurality of gate electrodes that extend from the memory cell region to the contact region and include pad portions which are end portions stacked in a step shape in the contact region; a plurality of contact plugs coupled to the pad portions of the gate electrodes; and a plurality of supporters formed below the pad portions of the gate electrodes.Type: GrantFiled: July 2, 2019Date of Patent: April 20, 2021Assignee: SK hynix Inc.Inventor: Dae-Sung Eom
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Publication number: 20210020658Abstract: A semiconductor device includes conductive patterns stacked and spaced apart from each other in a first direction to form a stepped structure, a stepped insulating layer overlapping the stepped structure, contact plugs extending through the stepped insulating layer in the first direction to contact respective contact portions of the conductive patterns, and barrier patterns disposed on sidewalls of the stepped insulating layer.Type: ApplicationFiled: September 24, 2020Publication date: January 21, 2021Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Patent number: 10818690Abstract: A semiconductor device includes conductive patterns stacked and spaced apart from each other in a first direction to form a stepped structure, a stepped insulating layer overlapping the stepped structure, contact plugs extending through the stepped insulating layer in the first direction to contact respective contact portions of the conductive patterns, and barrier patterns disposed on sidewalls of the stepped insulating layer.Type: GrantFiled: February 26, 2019Date of Patent: October 27, 2020Assignee: SK hynix Inc.Inventor: Dae Sung Eom
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Publication number: 20200152585Abstract: A vertical memory device includes: a substrate including a memory cell region and a contact region; a plurality of gate electrodes that extend from the memory cell region to the contact region and include pad portions which are end portions stacked in a step shape in the contact region; a plurality of contact plugs coupled to the pad portions of the gate electrodes; and a plurality of supporters formed below the pad portions of the gate electrodes.Type: ApplicationFiled: July 2, 2019Publication date: May 14, 2020Applicant: SK hynix Inc.Inventor: Dae-Sung EOM
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Publication number: 20200144391Abstract: A semiconductor device includes a first conductive pattern having a first line portion extending in a first direction and a first bending portion that extends from the first line portion. A closed area, surrounded by the first line portion and the first bending portion, is defined at one side of the first line portion. The semiconductor device further includes a second conductive pattern disposed in the closed area, the second conductive pattern being spaced apart from the first conductive pattern.Type: ApplicationFiled: June 12, 2019Publication date: May 7, 2020Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Patent number: 10559330Abstract: A memory device may include a first half memory block, a second half memory block, a row decoder group, and a read/write circuit which may be disposed between the first half memory block and the second half memory block. The read/write circuit may be coupled to the first half memory block and the second half memory block through a first bit line and a second bit line. The row decoder group may be configured to simultaneously select the first half memory block and the second half memory block in response to a single block selection signal.Type: GrantFiled: June 14, 2018Date of Patent: February 11, 2020Assignee: SK hynix Inc.Inventor: Dae Sung Eom
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Publication number: 20200027896Abstract: A semiconductor device includes conductive patterns stacked and spaced apart from each other in a first direction to form a stepped structure, a stepped insulating layer overlapping the stepped structure, contact plugs extending through the stepped insulating layer in the first direction to contact respective contact portions of the conductive patterns, and barrier patterns disposed on sidewalls of the stepped insulating layer.Type: ApplicationFiled: February 26, 2019Publication date: January 23, 2020Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Patent number: 10396168Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes a pipe gate stack structure in which a portion of a first channel layer is buried. The semiconductor device includes the pipe gate stack structure in which a portion of a second channel layer is buried. The semiconductor device configured to individually control the first and second channel layers.Type: GrantFiled: June 15, 2018Date of Patent: August 27, 2019Assignee: SK hynix Inc.Inventors: Dae Sung Eom, Jeong Sang Kang