Abstract: A resistor includes a first conductive layer; a second conductive layer protruding from the first conductive layer; a third conductive layer located above and facing the first conductive layer to face the first conductive layer; and at least two contact plugs electrically coupled to the third conductive layer.

Abstract: A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer.

Abstract: A resistor includes a first conductive layer; a second conductive layer protruding from the first conductive layer; a third conductive layer located above and facing the first conductive layer to face the first conductive layer; and at least two contact plugs electrically coupled to the third conductive layer.

Abstract: A resistor includes a first conductive layer; a second conductive layer protruding from the first conductive layer; a third conductive layer located above and facing the first conductive layer to face the first conductive layer; and at least two contact plugs electrically coupled to the third conductive layer.

Abstract: A semiconductor device includes at least 4 conductive line groups arranged in parallel over one memory cell block and each configured to include conductive lines. First contact pads may be coupled to the respective ends of the conductive lines of two of the 4 conductive line groups in a first direction, and second contact pads may be coupled to the respective ends of the conductive lines of the remaining 2 of the 4 conductive line groups in a second direction opposite to the first direction.

Abstract: A semiconductor device includes a semiconductor substrate configured to include a plurality of active regions that are stretched in parallel to each other, a plurality of first contact plugs and the plurality of active regions, wherein each active region is coupled with a corresponding first contact plug, and a contact pad configured to couple with a given number of first contact plugs among the plurality of first contact plugs. Misalignment occurring at the ends of a series of drain contacts may be prevented, and the size of well-pickup contacts may be decreased by forming contact plugs that are coupled with drain regions with the same distance to a well-pickup contact region without additionally forming well-pickup contact plugs and using the contact plugs as well-pickup contact plugs. Therefore, loss of a substrate may be minimized, and burden of Optical Proximity Correction (OPC) is relieved, reducing Turn-Around Time (TAT).

Abstract: A semiconductor device having a conductive pattern includes a plurality of conductive lines extending in parallel, each having a first region extending in a first direction and a second region coupled to the first region and extending in a second direction crossing the first direction, and a plurality of contact pads, each coupled to a respective conductive line of the second regions, wherein the conductive lines are grouped and arranged in a plurality of groups, the first region of a first group is longer than the first region of a second group, and the second region of the first group and the second region of the second group are spaced apart from each other.

Abstract: A semiconductor device includes a semiconductor substrate configured to include a plurality of active regions that are stretched in parallel to each other, a plurality of first contact plugs and the plurality of active regions, wherein each active region is coupled with a corresponding first contact plug, and a contact pad configured to couple with a given number of first contact plugs among the plurality of first contact plugs. Misalignment occurring at the ends of a series of drain contacts may be prevented, and the size of well-pickup contacts may be decreased by forming contact plugs that are coupled with drain regions with the same distance to a well-pickup contact region without additionally forming well-pickup contact plugs and using the contact plugs as well-pickup contact plugs. Therefore, loss of a substrate may be minimized, and burden of Optical Proximity Correction (OPC) is relieved, reducing Turn-Around Time (TAT).

Abstract: A semiconductor device includes at least 4 conductive line groups arranged in parallel over one memory cell block and each configured to include conductive lines. First contact pads may be coupled to the respective ends of the conductive lines of two of the 4 conductive line groups in a first direction, and second contact pads may be coupled to the respective ends of the conductive lines of the remaining 2 of the 4 conductive line groups in a second direction opposite to the first direction.

Abstract: A semiconductor device having a conductive pattern includes a plurality of conductive lines extending in parallel, each having a first region extending in a first direction and a second region coupled to the first region and extending in a second direction crossing the first direction, and a plurality of contact pads, each coupled to a respective conductive line of the second regions, wherein the conductive lines are grouped and arranged in a plurality of groups, the first region of a first group is longer than the first region of a second group, and the second region of the first group and the second region of the second group are spaced apart from each other.