Abstract: An electronic device includes an internal voltage generation circuit configured to detect a voltage level of an internal voltage, that is generated by the internal voltage generation circuit. The internal voltage generating circuit is also configured to generate a drive code, which, along with a drive clock, determines the magnitude of the generated internal voltage. The drive code may be reset responsive to the internal voltage. The electronic device also includes a load circuit which is powered by the generated internal voltage.

Abstract: An integrated circuit may include first to Nth data receiving circuits configured to receive, based on multi-phase clocks, first to Nth data through first to Nth data terminals to generate first to Nth multi-phase data, respectively, where N is an integer equal to or greater than 2; first to Nth delay circuits configured to delay first to Nth data having a selected phase, among the first to Nth multi-phase data, respectively; a clock delay circuit configured to delay a clock having the selected phase, among the multi-phase clocks; and a loopback circuit configured to transmit a clock delayed by the clock delay circuit to a loopback clock terminal, and transmit, based on the clock delayed by the clock delay circuit, one of first to Nth data having the selected phase, delayed by the first to Nth delay circuits, to a loopback data terminal.

Abstract: A signal transmission circuit includes a first latch driving circuit configured to latch a first alignment signal, based on a first division clock signal and a second division clock signal, and to drive a transmission signal, and a second latch driving circuit configured to latch a second alignment signal, based on the second division clock signal and a first inverted division clock signal, and to drive the transmission signal.

Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication and accumulation (MAC) units, each of the MAC units including a memory bank and a MAC operator, and a control circuit configured to control the plurality of MAC units to perform an all MAC mode operation in which MAC operations are performed in all MAC units, among the plurality of MAC units, or a dispersion MAC mode operation in which the MAC operations are performed in some MAC units, among the plurality of MAC units.

Abstract: A signal transmission circuit includes a first latch driving circuit configured to latch a first alignment signal, based on a first division clock signal and a second division clock signal, and to drive a transmission signal, and a second latch driving circuit configured to latch a second alignment signal, based on the second division clock signal and a first inverted division clock signal, and to drive the transmission signal.

Abstract: A test circuit may include: a plurality of replication receivers configured to generate a plurality of oscillation signal pairs in response to a plurality of oscillation enable signals; and an oscillation control circuit configured to generate the plurality of oscillation enable signals in response to a test enable signal, and to generate a detection signal in response to any one of the plurality of oscillation signal pairs.

Abstract: An electronic device includes an internal voltage generation circuit configured to detect a voltage level of an internal voltage, that is generated by the internal voltage generation circuit. The internal voltage generating circuit is also configured to generate a drive code, which, along with a drive clock, determines the magnitude of the generated internal voltage. The drive code may be reset responsive to the internal voltage. The electronic device also includes a load circuit which is powered by the generated internal voltage.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: A pipe register control signal generation circuit includes a sense amplifier configured to drive a global input/output line according to a result of sensing a voltage difference between a pair of local input/output lines according to a sense amplifier enable signal. The pipe register control signal generation circuit also includes a duplicate sense amplifier configured to simulate the sense amplifier and configured to generate a pipe register control signal according to a result of sensing a difference between a first voltage and a second voltage according to the sense amplifier enable signal.

Abstract: A semiconductor chip includes a first input/output control circuit configured to generate a first input/output switching signal that controls a first data input/output operation on a first data input/output group according to a first input voltage generated based on an operation voltage, and a second input/output control circuit configured to generate a second input/output switching signal that controls a second data input/output operation on a second data input/output group according to a second input voltage generated based on the operation voltage.

Abstract: A test circuit may include: a plurality of replication receivers configured to generate a plurality of oscillation signal pairs in response to a plurality of oscillation enable signals; and an oscillation control circuit configured to generate the plurality of oscillation enable signals in response to a test enable signal, and to generate a detection signal in response to any one of the plurality of oscillation signal pairs.

Abstract: A semiconductor device includes a strobe transmission circuit configured to output an oscillation strobe signal, through a first delay path circuit, as a strobe signal when a first measurement operation is performed and configured to output the oscillation strobe signal through a second delay path circuit as the strobe signal when a second measurement operation is performed, and a calibration circuit configured to compare the number of times the strobe signal toggles during the first measurement operation to the number of times the strobe signal toggles during the second measurement operation to calibrate the delay amounts of the first and second delay path circuits to be the same.

Abstract: A memory core includes a first signal line; a second signal line; a first transistor coupled between the second signal line and a data storage element; a second transistor coupled between the first signal line and the data storage element; and a switching circuit configured to, in response to a mode selection signal, switch an operation of the memory core between a first mode and a second mode, the first mode controlling the first transistor according to a level of the first signal line and turning off the second transistor and a second mode controlling the second transistor according to a level of the second signal line and turning off the first transistor.

Abstract: A pipe register control signal generation circuit includes a sense amplifier configured to drive a global input/output line according to a result of sensing a voltage difference between a pair of local input/output lines according to a sense amplifier enable signal. The pipe register control signal generation circuit also includes a duplicate sense amplifier configured to simulate the sense amplifier and configured to generate a pipe register control signal according to a result of sensing a difference between a first voltage and a second voltage according to the sense amplifier enable signal.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: A semiconductor device includes a strobe transmission circuit configured to output an oscillation strobe signal, through a first delay path circuit, as a strobe signal when a first measurement operation is performed and configured to output the oscillation strobe signal through a second delay path circuit as the strobe signal when a second measurement operation is performed, and a calibration circuit configured to compare the number of times the strobe signal toggles during the first measurement operation to the number of times the strobe signal toggles during the second measurement operation to calibrate the delay amounts of the first and second delay path circuits to be the same.

Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication and accumulation (MAC) units, each of the MAC units including a memory bank and a MAC operator, and a control circuit configured to control the plurality of MAC units to perform an all MAC mode operation in which MAC operations are performed in all MAC units, among the plurality of MAC units, or a dispersion MAC mode operation in which the MAC operations are performed in some MAC units, among the plurality of MAC units.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: A duobinary receiver includes a signal dividing circuit configured to output a plurality of data by dividing an input signal according to a plurality of multi-phase sampling clocks signals; a level detecting circuit configured to output a plurality of state signals respectively corresponding to duobinary levels of the plurality of data; and a data converting circuit configured to decode the plurality of state signals to output a corresponding plurality of bits.

Abstract: A semiconductor apparatus receives a first clock signal and a second clock signal. The semiconductor apparatus configured to perform a training operation internally, the training operation being an operation of internally correcting a phase difference between the first clock signal and the second clock signal by dividing the first clock signal to generate multi-phase signals, detecting phase difference between the second clock signal and the multi-phase signals, and adjusting phases of the multi-phase signals according to a result of the detecting of the phase difference.