Abstract: A pipe register control signal generation circuit includes a sense amplifier configured to drive a global input/output line according to a result of sensing a voltage difference between a pair of local input/output lines according to a sense amplifier enable signal. The pipe register control signal generation circuit also includes a duplicate sense amplifier configured to simulate the sense amplifier and configured to generate a pipe register control signal according to a result of sensing a difference between a first voltage and a second voltage according to the sense amplifier enable signal.

Abstract: A semiconductor chip includes a first input/output control circuit configured to generate a first input/output switching signal that controls a first data input/output operation on a first data input/output group according to a first input voltage generated based on an operation voltage, and a second input/output control circuit configured to generate a second input/output switching signal that controls a second data input/output operation on a second data input/output group according to a second input voltage generated based on the operation voltage.

Abstract: The present invention relates to a non-coating thermoplastic resin composition, a method for manufacturing a molded article by using the same, and a molded article manufactured by the same. More specifically, the present invention is characterized by providing the thermoplastic resin composition which contains polycarbonate, polysiloxane-polycarbonate copolymer, polyester, master-batched carbon black, and additives in specific contents and the molded article, which has excellent chemical resistance, mechanical properties, light resistance, hydrolysis resistance, and low glossiness, manufactured by using the same.

Abstract: A test circuit may include: a plurality of replication receivers configured to generate a plurality of oscillation signal pairs in response to a plurality of oscillation enable signals; and an oscillation control circuit configured to generate the plurality of oscillation enable signals in response to a test enable signal, and to generate a detection signal in response to any one of the plurality of oscillation signal pairs.

Abstract: A semiconductor device includes a strobe transmission circuit configured to output an oscillation strobe signal, through a first delay path circuit, as a strobe signal when a first measurement operation is performed and configured to output the oscillation strobe signal through a second delay path circuit as the strobe signal when a second measurement operation is performed, and a calibration circuit configured to compare the number of times the strobe signal toggles during the first measurement operation to the number of times the strobe signal toggles during the second measurement operation to calibrate the delay amounts of the first and second delay path circuits to be the same.

Abstract: A memory core includes a first signal line; a second signal line; a first transistor coupled between the second signal line and a data storage element; a second transistor coupled between the first signal line and the data storage element; and a switching circuit configured to, in response to a mode selection signal, switch an operation of the memory core between a first mode and a second mode, the first mode controlling the first transistor according to a level of the first signal line and turning off the second transistor and a second mode controlling the second transistor according to a level of the second signal line and turning off the first transistor.

Abstract: A pipe register control signal generation circuit includes a sense amplifier configured to drive a global input/output line according to a result of sensing a voltage difference between a pair of local input/output lines according to a sense amplifier enable signal. The pipe register control signal generation circuit also includes a duplicate sense amplifier configured to simulate the sense amplifier and configured to generate a pipe register control signal according to a result of sensing a difference between a first voltage and a second voltage according to the sense amplifier enable signal.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: A semiconductor device includes a strobe transmission circuit configured to output an oscillation strobe signal, through a first delay path circuit, as a strobe signal when a first measurement operation is performed and configured to output the oscillation strobe signal through a second delay path circuit as the strobe signal when a second measurement operation is performed, and a calibration circuit configured to compare the number of times the strobe signal toggles during the first measurement operation to the number of times the strobe signal toggles during the second measurement operation to calibrate the delay amounts of the first and second delay path circuits to be the same.

Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication and accumulation (MAC) units, each of the MAC units including a memory bank and a MAC operator, and a control circuit configured to control the plurality of MAC units to perform an all MAC mode operation in which MAC operations are performed in all MAC units, among the plurality of MAC units, or a dispersion MAC mode operation in which the MAC operations are performed in some MAC units, among the plurality of MAC units.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: A duobinary receiver includes a signal dividing circuit configured to output a plurality of data by dividing an input signal according to a plurality of multi-phase sampling clocks signals; a level detecting circuit configured to output a plurality of state signals respectively corresponding to duobinary levels of the plurality of data; and a data converting circuit configured to decode the plurality of state signals to output a corresponding plurality of bits.

Abstract: A semiconductor apparatus receives a first clock signal and a second clock signal. The semiconductor apparatus configured to perform a training operation internally, the training operation being an operation of internally correcting a phase difference between the first clock signal and the second clock signal by dividing the first clock signal to generate multi-phase signals, detecting phase difference between the second clock signal and the multi-phase signals, and adjusting phases of the multi-phase signals according to a result of the detecting of the phase difference.

Abstract: A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

Abstract: A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

Abstract: A transceiver includes a duobinary conversion circuit configured to determine a level of an input signal which is a duobinary signal according to an intermediate voltage, a first reference voltage higher than the intermediate voltage, and a second reference voltage lower than the intermediate voltage, and to convert the input signal into a non-return-to-zero (NRZ) signal; and a control circuit configured to generate one or more control signals to substantially remove inter-symbol interference (ISI) between symbols of the input signal, and to adjust the first reference voltage, or the second reference voltage, or both according to the level of the input signal.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

Abstract: A clock distribution circuit may include a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal; and a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to be input a power source voltage and configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit, wherein a first bias voltage provided to the first circuit and a second bias voltage provided to the second circuit are controlled independently of each other.

Abstract: A transmitter provides a duobinary signal corresponding to one of level 0, level 1, and level 2 based on first data and second data, and includes a pull-up driving circuit including a plurality of pull-up resistors selectively coupled between a first power source and a transmission node according to the first data and the second data; and a pull-down driving circuit including a plurality of pull-down resistors selectively coupled between the transmission node and a second power source, wherein at least one of the plurality of pull-up resistors is coupled between the first power source and the transmission node both when the first data is activated and when the second data is activated, or at least one of the plurality of pull-down resistors is coupled between the second power source and the transmission node both when the first data is activated and when the second data is activated.