Abstract: A channel tuning method and a television using a channel name auto completion function in which the entire channel name of a corresponding channel is automatically completed by inputting part of a channel name of a television broadcasting channel to be tuned using a predetermined inputting unit. The channel tuning method includes (a) searching similar channel names based on one or more of the characters of a channel name input by the inputting unit and displaying the searched channel names on a list from which selections can be made, and (b) in order to aid a user in selecting a channel, automatically tuning a corresponding channel among channels corresponding to the channel names displayed on the list for a predetermined interval of time and sequentially displaying the channels on a picture-in-picture (PIP) screen.

Abstract: A portable computer includes a main LCD panel hingedly coupled to a system body, and an auxiliary LCD panel mounted upon the system body. A video image is identically displayed on both the main LCD panel and the auxiliary LCD panel. Alternatively, a definition of the auxiliary LCD panel is lower than that of the main LCD panel. Although a user cannot look at a screen of the main LCD panel, the user can confirm a position of a pointer through a screen of the auxiliary LCD panel. Therefore, the user can precisely control the pointer using a touch screen.

Abstract: A channel tuning method and a television using a channel name auto completion function in which the entire channel name of a corresponding channel is automatically completed by inputting part of a channel name of a television broadcasting channel to be tuned using a predetermined inputting unit. The channel tuning method includes (a) searching similar channel names based on one or more of the characters of a channel name input by the inputting unit and displaying the searched channel names on a list from which selections can be made, and (b) in order to aid a user in selecting a channel, automatically tuning a corresponding channel among channels corresponding to the channel names displayed on the list for a predetermined interval of time and sequentially displaying the channels on a picture-in-picture (PIP) screen.

Abstract: A color projector for correcting chromatism by changing the sizes or positions of three display devices with respect to each color is provided. In the color projector, two or more display devices selected from the first through third display devices have different sizes of effective areas where an image is formed such that chromatism generated while lights of different colors synthesized by the synthesizing device pass the projection lens unit can be corrected. Also, the distances between two or more display devices selected from the first through third display devices and the projection lens unit are different from one another such that chromatism generated while lights of different colors synthesized by the synthesizing device pass the projection lens unit can be corrected.

Abstract: A micro-mirror device and associated method, the device including a substrate, address electrodes provided on the substrate, and a micro-mirror facing the substrate and spaced a predetermined distance from the substrate. The micro-mirror device is adapted so that the slope of the micro-mirror can be adjusted by electrostatic attraction forces between the address electrodes and the micro-mirror. The micro-mirror device further includes auxiliary electrodes formed on and projected from the substrate. The upper portions of the auxiliary electrodes are disposed in the vicinity of the micro-mirror, so that distances between the micro-mirror and the auxiliary electrodes can remain small, even when the micro-mirror is inclined by electrostatic attraction forces in one direction. Accordingly, restoration of the micro-mirror is enhanced by electrostatic attraction forces of the auxiliary electrodes.

Abstract: An LCD device has a distorted and/or curved shape corresponding to an image formed on the screen before correcting for distortion and/or curvature of the image formed on the screen, which are generated due to distortion aberration and/or curvature aberration of the projection lens unit, so that distortion and/or curvature can be corrected. The LCD device has a pin-cushion type structure distorted and curved positively (+) so that negative (−) distortion and curvature of the image formed on the screen, which is generated due to distortion aberration and curvature aberration of the projection lens unit, can be corrected. Also, the LCD device includes a front substrate and a rear substrate, each having electrodes formed thereon, and the front substrate and/or the rear substrate have a pin-cushion shape distorted and/or curved positively (+).

Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

Abstract: A graphic RAM array has a plurality of sub blocks which share random and serial output paths. This structure enables random access to the random output path of one RAM array while a specific sub block of another other RAM array is performing a display operation via the serial output path. The graphic RAM does not have a separate data register and outputs the serial data using only the RAM array. Thus, only the RAM array is formed in the cell core region, thereby reducing the size and price of the chip. In addition, it is possible for the graphic RAM to be compatible with a system having a conventional video RAM controller.

Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

Abstract: The present invention provides an electrostatic discharge protection device of a semiconductor memory device which comprises a gate and a bulk region of first conduction type which are commonly connected to a first power supply, a first diffused region of second conduction type formed in the bulk region, isolated from the gate by a dielectric and connected to the second power supply, and a second diffused region of second conduction type separated from the first diffused region in the bulk region, isolated from the gate by the dielectric and connected to the signal voltage.

Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

Abstract: There is disclosed a memory cell made with a semiconductor substrate for mounting integrated circuit elements, and having a trench for forming a capacitor region extending vertically to the surface of the substrate. In the substrate region around the trench is formed a cell plate region of second conductivity type for forming a charge storage region within the capacitor region. A high concentration semiconductor region of the same conductivity type as the substrate is formed in the substrate region outside the cell plate region to increase the charge stored in the capacitor region. A conducting material stores charge responding to the voltage given within the trench. A dielectric layer is formed between the conducting material and the cell plate.

Abstract: A circuit is provided for protecting the internal circuit of a semiconductor device from electrostatic discharge (ESD). This circuit includes an input pad for applying an input signal to the internal circuit, a metal line for electrically connecting the input pad and internal circuit. This metal line has at least one RC delay stage caused by inherent parasitic resistances and capacitances. Also, a punch-through element is provided to connect the metal line to a ground voltage terminal disposed between the input pad and a delay stage. Finally, a resistor is used to connect the at least one delay stage to the internal circuit.

Abstract: A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three factors in increasing the effective area for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterened to selectively remove the storage poly layer, and the spacer maximizes the size of the storage poly; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a plat poly material is coated and wrapped.

Abstract: A row redundancy circuit for use in a semiconductor memory device. The row redundancy circuit providing fuse boxes to repair defective normal memory cells even in the adjacent normal memory cell arrays.

Abstract: The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory for accomplishing high speed data access by supplying a plurality of row address strobe signals to a chip. A plurality of row address strobe signals are supplied to a plurality of pins, and each row address strobe signal is sequentially supplied with an active signal during a data access operation. Therefore, data in a plurality of memory cell arrays is accessed during one access cycle time. Thus, since a large number of random data are provided, the data access time decreases and the performance of a system can be greatly improved.

Abstract: A method for manufacturing a VLSI semiconductor memory device, in which a cell transistor is formed in the cell array section of a semiconductor substrate, successively, a cell capacitor. Then, a transistor is formed in the periphery circuit section of the substrate. Therefore, access transistors of the cell array section are formed independently from transistors of the peripheral circuit section, optimizing transistor performance.

Abstract: A data transmission circuit capable of a high-speed data input/output operation and a large-scaled integration for use in a semiconductor memory device, is disclosed. The data transmission circuit has at least one memory cell 51, a word line 52, a pair of bit lines 65, 66, a sense amplifier 55, and a pair of isolation transistors 53, 54. Further, the circuit includes a pair of common input/output lines 67, 68 for transmitting input or output data with a complementary logic operation, a discharging transistor 56 receiving a control signal at its gate and having a channel connected with a ground voltage node, for transferring an electric potential applied to one end of the channel into the ground voltage level, and a pair of transmission transistors 59, 60 receiving the control signal at their respective gates and having each channel connected with the common input/output lines.

Abstract: A sense amplifier driving circuit for controlling sense amplifiers of high density semiconductor memory device by turning-on/off a driving transistor connected between an external voltage Vcc terminal and a ground voltage Vss terminal, comprises a bias circuit including a MOS transistor being connected to the driving MOS transistor to form a current mirror circuit therewith which is controlled by a sense amplifier enable clock and a constant current source having a MOS transistor with a bias voltage of an intermediate level between Vcc and Vss being applied to its gate terminal. The bias circuit is connected to the gate terminal of the driving transistor to control the gate voltage of the driving transistor, thereby reducing the peak current of a sense amplifier driving signal. Further, the driving signals are generated in the waveform having a linear dual slope, resulting in a decrease in power-noise.

Abstract: A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three factors in increasing the effective area for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterened to selectively remove the storage poly layer, and the spacer maximizes the size of the storage poly; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a .?.plat.!. .Iadd.plate .Iaddend.poly material is coated and wrapped.