Stack capacitor DRAM cell having increased capacitor area

Claims

3. The DRAM according to claim 1 wherein said second portion of said storage polysilicon layer is substantially uniform in thickness.

4. The DRAM according to claim 2 wherein said second portion of said storage polysilicon layer is substantially uniform in thickness.

9. A semiconductor memory device, comprising:

a semiconductor substrate having a gate electrode formed thereon with said gate electrode having an insulating layer formed thereon;

a first capacitive electrode layer formed on said insulating layer, said first capacitive electrode layer having an edge portion spaced apart from said insulating layer thereby exposing a partial lower surface of said first capacitive electrode layer at said edge portion;

a dielectric layer formed on said first capacitive electrode layer, said dielectric layer wrapping around and under said edge portion and substantially along said partial lower surface of said first capacitive electrode layer; and

a second capacitive electrode layer formed on said dielectric layer, said second capacitive layer wrapping around and under said edge portion, whereby said second capacitive electrode layer extends between said dielectric layer and said insulating layer..Iaddend..Iadd.

10. The semiconductor device of claim 9, wherein said partial lower surface of said first capacitive electrode layer and said insulating layer define an undercut region under said first capacitive electrode layer..Iaddend..Iadd.11. The semiconductor device of claim 10, wherein said undercut region is of variable size..Iaddend..Iadd.12. The semiconductor device of claim 9, wherein said partial lower surface defines inner and outer ends of said edge portion extending over said gate electrode..Iaddend..Iadd.13. The semiconductor device of claim 12, wherein said inner and outer ends of said edge portion terminate within a vertical plane defined by first and second sides of the gate electrode..Iaddend..Iadd.14. The semiconductor device of claim 13, wherein the outer end of said edge portion extends a first lateral distance over said gate electrode and said inner end of said edge portion extends a second lesser distance over said gate electrode..Iaddend..Iadd.15. The semiconductor device of claim 12, wherein said inner end of said edge portion terminates within a vertical plane defined by first and second sides of the gate electrode, and said outer end of said edge portion terminates outside of the vertical plane defined by the first and second sides of the gate

electrode..Iaddend..Iadd.16. A semiconductor memory device, comprising:

a semiconductor substrate having a gate electrode formed thereon with said gate electrode having an insulating layer formed thereon, wherein said insulating layer is a laminated insulating layer comprising a plurality of laminae;

a first capacitive electrode layer formed on said insulating layer, said first capacitive electrode layer having an edge portion spaced apart from said insulating layer thereby exposing a partial lower surface of said first capacitive electrode layer at said edge portion;

a dielectric layer formed on said first capacitive electrode layer, said dielectric layer wrapping around and under said edge portion and substantially along said partial lower surface of said first capacitive electrode layer; and

a second capacitive electrode layer formed on said dielectric layer, said second capacitive layer wrapping around and under said edge portion, whereby said second capacitive electrode layer extends between said

dielectric layer and said insulating layer..Iaddend..Iadd.17. A stacked capacitor as in claim 16, wherein said insulating layer comprises upper, center and lower lamina..Iaddend..Iadd.18. A stacked capacitor as in claim 17, wherein an insulating material of said center lamina is different than an insulating material of said upper lamina..Iaddend..Iadd.19. A stacked capacitor as in claim 18, wherein said insulating material of said center lamina is nitride and said insulating material of said upper lamina is oxide..Iaddend..Iadd.20. A stacked capacitor as in claim 19, wherein said insulating material of said lower lamina is oxide..Iaddend..Iadd.21. A stacked capacitor as in claim 19, wherein said comprising a conductive member disposed beneath said first capacitive electrode layer, and wherein said center lamina of said insulating layer insulates a portion of said second capacitive electrode layer extending beneath said first capacitive electrode layer from said second capacitive electrode layer..Iaddend..Iadd.22. A stacked capacitor as in claim 9, wherein said partial lower surface defines an undercut

extending over said gate electrode..Iaddend..Iadd.23. A stacked capacitor as in claim 9, wherein said partial lower surface defines an undercut extending over a word line..Iaddend..Iadd.24. A stacked capacitor as in claim 9, having at least one of a partial lower surface defining a first undercut extending over said gate electrode, and a partial lower surface defining a second undercut extending over a word line..Iaddend..Iadd.25. A stacked capacitor as in claim 9, having a partial lower surface defining a first undercut extending over said gate electrode, and a partial lower surface defining a second undercut extending over a word line..Iaddend..Iadd.26. A semiconductor memory device, comprising:

a semiconductor substrate having a gate electrode formed thereon with said gate electrode having an insulating layer formed thereon;

a first capacitive electrode layer having a first portion formed on said insulating layer and a second portion having an edge portion spaced apart from said insulating layer thereby exposing a partial lower surface of said first capacitive electrode layer at said edge portion;

a dielectric layer formed on said first capacitive electrode layer, said dielectric layer wrapping around and under said edge portion and substantially along said partial lower surface of said first capacitive electrode layer; and

a second capacitive electrode layer formed on said dielectric layer, said second capacitive layer wrapping around and under said edge portion, whereby said second capacitive electrode layer extends between said dielectric layer and said insulating layer..Iaddend..Iadd.27. A stacked capacitor as in claim 26, wherein said first portion of said first capacitive electrode layer is substantially uniform in thickness.

.Iaddend..Iadd.28. A stacked capacitor as in claim 26, wherein said second portion of said first capacitive electrode layer is substantially uniform in thickness..Iaddend..Iadd.29. A stacked capacitor as in claim 28, said first portion having a greater thickness than said second portion..Iaddend..Iadd.30. A stacked capacitor DRAM formed on a substrate comprising a plurality of memory cells on said substrate, each of said cells comprising a charge transfer transistor and a stacked capacitor, said stacked capacitor comprising:

a laminated insulating layer terminating in a side edge;

a storage polysilicon layer for said capacitor including a first portion disposed on said insulating layer and a second portion extending beyond the side edge thereof, said second portion extending to and overlying a gate of said charge transfer transistor,

said polysilicon layer terminating in a side edge, and including a conductive layer separated from said polysilicon layer by a dielectric layer, said conductive and dielectric layers extending over an upper surface of said polysilicon layer, along said side edge thereof, and beneath a section of said polysilicon layer, an edge of said insulating layer being disposed beneath and inwardly of said side edge of said polysilicon layer thereby providing a space between a bottom surface portion of said polysilicon layer and a top surface portion of said insulating layer, and said space being filled with the portions of said conductive and dielectric layers extending beneath said polysilicon layer whereby said conductive and dielectric layers do not surround said storage polysilicon layer..Iaddend..Iadd.31. A stacked capacitor as in claim 30, said laminated insulating layer comprising a plurality of laminae..Iaddend..Iadd.32. A stacked capacitor as in claim 31, wherein said insulating layer comprises upper, center and lower lamina.

.Iaddend..Iadd. 3. A stacked capacitor as in claim 32, wherein an insulating material of said center lamina is different than an insulating material of said upper lamina..Iaddend..Iadd.34. A stacked capacitor as in claim 33, wherein said insulating material of said center lamina is nitride and said insulating material of said upper lamina is oxide..Iaddend..Iadd.35. A stacked capacitor as in claim 34, wherein said insulating material of said lower lamina is oxide..Iaddend..Iadd.36. A stacked capacitor as in claim 32, further comprising a conductive member disposed beneath said polysilicon layer, and wherein said center lamina of said insulating layer insulated a portion of said conductive member extending beneath said polysilicon layer from said conductive member..Iaddend..Iadd.37. A stacked capacitor as in claim 30, wherein said space, between the bottom surface portion of said first portion of said polysilicon layer and the top surface portion of said insulating layer, defines an undercut overlying a word line..Iaddend..Iadd.38. A stacked capacitor as in claim 30, wherein said space, between the bottom surface portion of said second portion of said polysilicon layer and the top surface portion of said insulating layer, defines an undercut overlying the gate of said charge transfer transistor..Iaddend..Iadd.39. A stacked capacitor as in claim 30, having at least one of

said space between the bottom surface portion of said first portion of said polysilicon layer and the top surface portion of said insulating layer, defining a first undercut overlying a word line, and

said space between the bottom surface portion of said second portion of said polysilicon layer and the top surface portion of said insulating layer, defining a second undercut overlying the gate of said charge

transfer transistor..Iaddend..Iadd.40. A stacked capacitor as in claim 30, having said space between the bottom surface portion of said first portion of said polysilicon layer and the top surface portion of said insulating layer, defining a first undercut overlying a word line, and

said space between the bottom surface portion of said second portion of said polysilicon layer and the top surface portion of said insulating layer, defining a second undercut overlying the gate of said charge transfer transistor..Iaddend..Iadd.41. A stacked capacitor as in claim 30, wherein said first portion of said polysilicon layer is substantially uniform in thickness..Iaddend..Iadd.42. A stacked capacitor as in claim 41, wherein said second portion of said polysilicon layer is substantially uniform in thickness..Iaddend..Iadd.43. A stacked capacitor as in claim 42, said first portion having a greater thickness than said second portion..Iaddend.