Patents by Inventor Daewoong Suh

Daewoong Suh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Forming a semiconductor package including a thermal interface material
    Patent number: 8409929
    Abstract: In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 2, 2013
    Assignee: Intel Corporation
    Inventors: Mukul Renavikar, Daewoong Suh, Carl Deppisch, Abhishek Gupta
  • Microelectronic package with self-heating interconnect
    Patent number: 8378504
    Abstract: A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate and a die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: February 19, 2013
    Assignee: Intel Corporation
    Inventor: Daewoong Suh
  • Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same
    Patent number: 8344483
    Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: January 1, 2013
    Assignee: Intel Corporation
    Inventors: Nachiket Raravikar, Daewoong Suh
  • METHODS OF FORMING CARBON NANOTUBES ARCHITECTURES AND COMPOSITES WITH HIGH ELECTRICAL AND THERMAL CONDUCTIVITES AND STRUCTURES FORMED THEREBY
    Publication number: 20120148842
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include method of forming a layered nanotube structure comprising a wetting layer disposed on a nanotube, a Shottky layer disposed on the wetting layer, a barrier layer disposed on the Shottky layer, and a matrix layer disposed on the barrier layer.
    Type: Application
    Filed: February 13, 2012
    Publication date: June 14, 2012
    Inventors: Nachiket Raravikar, Daewoong Suh, Chris Matayabas
  • Methods of fabricating robust integrated heat spreader designs and structures formed thereby
    Patent number: 8174113
    Abstract: Methods and associated structures of forming an indium containing solder material directly on an active region of a copper IHS is enabled. A copper indium containing solder intermetallic is formed on the active region of the IHS. The solder intermetallic improves the solder-TIM integration process for microelectronic packaging applications.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: May 8, 2012
    Assignee: Intel Corporation
    Inventors: Abhishek Gupta, Mike Boyd, Carl Deppisch, Jinlin Wang, Daewoong Suh, Brad Drew
  • Methods of forming carbon nanotubes architectures and composites with high electrical and thermal conductivities and structures formed thereby
    Patent number: 8158968
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include method of forming a layered nanotube structure comprising a wetting layer disposed on a nanotube, a Shottky layer disposed on the wetting layer, a barrier layer disposed on the Shottky layer, and a matrix layer disposed on the barrier layer.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: April 17, 2012
    Assignee: Intel Corporation
    Inventors: Nachiket Raravikar, Daewoong Suh, Chris Matayabas
  • Method of forming an interconnect joint
    Patent number: 8124517
    Abstract: A method of forming an interconnect joint includes providing a first metal layer (210, 310), providing a film (220, 320) including metal particles (221, 321) and organic molecules (222, 322), placing the film over the first metal layer, placing a second metal layer (230, 330) over the film, and sintering the metal particles such that the organic molecules degrade and the first metal layer and the second metal layer are joined together.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: February 28, 2012
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, Daewoong Suh
  • Carbon nanotubes solder composite for high performance interconnect
    Patent number: 8100314
    Abstract: An embodiment of the present invention is an interconnect technique. Carbon nanotubes (CNTs) are prepared. A CNT-solder composite paste is formed containing the CNTs and solder with a pre-defined volume fraction.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: January 24, 2012
    Assignee: Intel Corporation
    Inventor: Daewoong Suh
  • Forming A Semiconductor Package Including A Thermal Interface Material
    Publication number: 20110312131
    Abstract: In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed.
    Type: Application
    Filed: August 30, 2011
    Publication date: December 22, 2011
    Inventors: Mukul Renavikar, Daewoong Suh, Carl Deppisch, Abhishek Gupta
  • Forming a semiconductor package including a thermal interface material
    Patent number: 8030757
    Abstract: In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: October 4, 2011
    Assignee: Intel Corporation
    Inventors: Mukul Renavikar, Daewoong Suh, Carl Deppisch, Abhishek Gupta
  • Solder joint reliability in microelectronic packaging
    Patent number: 8018063
    Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: September 13, 2011
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Stephen E. Lehman, Jr., Mukul Renavikar
  • Inductor using bulk metallic glass material
    Patent number: 7986209
    Abstract: Inductors using bulk metallic glass (BMG) material and associated methods are generally described. In one example, an apparatus includes an electrically conductive core material, an electrically insulative material coupled with the electrically conductive core material, and a magnetic bulk metallic glass (BMG) material coupled with the electrically insulative material, wherein the electrically conductive core material, the electrically insulative material, and the magnetic BMG material form an inductor.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: July 26, 2011
    Assignee: Intel Corporation
    Inventors: Chang-min Park, Daewoong Suh
  • Process for joining materials using bulk metallic glasses
    Patent number: 7947134
    Abstract: Methods and compositions for a novel metal-to-metal or material-to-material joining technique using bulk metallic glasses are provided. The method of the current invention relies on the superior mechanical properties of bulk metallic glasses and/or softening behavior of metallic glasses in the undercooled liquid region of temperature-time process space, enabling joining of a variety of materials at a much lower temperature than typical ranges used for soldering, brazing or welding.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: May 24, 2011
    Assignee: California Institute of Technology
    Inventors: Boonrat Lohwongwatana, Robert D. Conner, Jin-Yoo Suh, William L. Johnson, Daewoong Suh
  • SOLDER JOINT RELIABILITY IN MICROELECTRONIC PACKAGING
    Publication number: 20110051376
    Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.
    Type: Application
    Filed: November 8, 2010
    Publication date: March 3, 2011
    Applicant: INTEL, INC.
    Inventors: Daewoong Suh, Stephen E. Lehman, JR., Mukul Renavikar
  • Methods and apparatuses for providing stacked-die devices
    Patent number: 7867818
    Abstract: Methods and apparatuses to provide a stacked-die device comprised of stacked sub-packages. For one embodiment of the invention, each sub-package has interconnections formed on the die-side of the substrate for interconnecting to another sub-package. The dies and associated wires are protected by an encapsulant leaving an upper portion of each interconnection exposed. For one embodiment of the invention the encapsulant is a stencil-printable encapsulant and the upper portion of the interconnection is exposed by use of a patterned stencil during application of the encapsulant.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: January 11, 2011
    Inventors: Daewoong Suh, Debendra Mallik
  • METHOD OF FORMING AN INTERCONNECT JOINT
    Publication number: 20100276474
    Abstract: A method of forming an interconnect joint includes providing a first metal layer (210, 310), providing a film (220, 320) including metal particles (221, 321) and organic molecules (222, 322), placing the film over the first metal layer, placing a second metal layer (230, 330) over the film, and sintering the metal particles such that the organic molecules degrade and the first metal layer and the second metal layer are joined together.
    Type: Application
    Filed: July 16, 2010
    Publication date: November 4, 2010
    Inventors: Lakshmi Supriya, Daewoong Suh
  • CARBON NANOTUBE-SOLDER COMPOSITE STRUCTURES FOR INTERCONNECTS, PROCESS OF MAKING SAME, PACKAGES CONTAINING SAME, AND SYSTEMS CONTAINING SAME
    Publication number: 20100219511
    Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.
    Type: Application
    Filed: May 11, 2010
    Publication date: September 2, 2010
    Inventors: Nachiket Raravikar, Daewoong Suh
  • Carbon nanotube coated capacitor electrodes
    Publication number: 20100177475
    Abstract: Devices and methods for their formation, including electronic devices containing capacitors, are described. In one embodiment, a device includes a substrate and a capacitor is formed on the substrate. The capacitor includes first and second electrodes and a capacitor dielectric between the first and second electrodes. At least one of the first and second electrodes includes a metal layer having carbon nanotubes coupled thereto. In one aspect of certain embodiments, the carbon nanotubes are at least partially coated with an electrically conductive material. In another aspect of certain embodiments, the substrate comprises an organic substrate and the capacitor dielectric comprises a polymer material. Other embodiments are described and claimed.
    Type: Application
    Filed: March 19, 2010
    Publication date: July 15, 2010
    Inventors: Yongki Min, Daewoong Suh
  • Solder foams, nano-porous solders, foamed-solder bumps in chip packages, methods of assembling same, and systems containing same
    Patent number: 7745013
    Abstract: A foamed solder or a nano-porous solder is formed on a substrate of an integrated circuit package. The foamed solder exhibits a low modulus that resists cracking during shock and dynamic loading. The foamed solder is used as a solder bump for communication between an integrated circuit device and external structures.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: June 29, 2010
    Assignee: Intel Corporation
    Inventors: Heeman Choe, Daewoong Suh
  • Microelectronic package interconnect and method of fabrication thereof
    Patent number: 7727814
    Abstract: A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: June 1, 2010
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Amram Eitan, Yongki Min