Patents by Inventor Daewoong Suh

Daewoong Suh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7727815
    Abstract: A method for forming a high thermal conductivity heat sink to IC package interface is disclosed. The method uses reactive getter materials added to a two phase solder system having a phase change temperature that is about the normal operating temperature range of the IC, to bind absorbed and dissolved oxygen in the two phase solder interface material at or near the air to solder surface. Over time this chemical binding action results in an oxide layer at the air to solder surface that slows the rate of oxygen absorption into the solder interface material, and thus reduces the harmful oxidation of the solder to IC package interface and the solder to heat sink interface.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: June 1, 2010
    Assignee: Intel Corporation
    Inventors: Chad A. Kumaus, Carl Deppisch, Daewoong Suh, Ashay A. Dani
  • Publication number: 20100126631
    Abstract: An embodiment of the present invention is an interconnect technique. Carbon nanotubes (CNTs) are prepared. A CNT-solder composite paste is formed containing the CNTs and solder with a pre-defined volume fraction.
    Type: Application
    Filed: January 19, 2010
    Publication date: May 27, 2010
    Applicant: INTEL CORPORATION
    Inventor: Daewoong Suh
  • Patent number: 7713858
    Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Nachiket Raravikar, Daewoong Suh
  • Patent number: 7710709
    Abstract: Devices and methods for their formation, including electronic devices containing capacitors, are described. In one embodiment, a device includes a substrate and a capacitor is formed on the substrate. The capacitor includes first and second electrodes and a capacitor dielectric between the first and second electrodes. At least one of the first and second electrodes includes a metal layer having carbon nanotubes coupled thereto. In one aspect of certain embodiments, the carbon nanotubes are at least partially coated with an electrically conductive material. In another aspect of certain embodiments, the substrate comprises an organic substrate and the capacitor dielectric comprises a polymer material. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Yongki Min, Daewoong Suh
  • Patent number: 7705458
    Abstract: A foamed bulk metallic glass electrical connection is formed on a substrate of an integrated circuit package. The foamed bulk metallic glass electrical connection exhibits a low modulus that resists cracking during shock and dynamic loading. The foamed bulk metallic glass electrical connection is used as a solder bump for communication between an integrated circuit device and external structures. A process of forming the foamed bulk metallic glass electrical connection includes mixing bulk metallic glass with a blowing agent.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Yongki Min
  • Patent number: 7699210
    Abstract: In some example embodiments, a method includes engaging a first contact on a motherboard with a second contact on an electronic package. A portion of one of the first and second contacts is covered with an interlayer that has a lower melting temperature than both of the first and second contacts. The method further includes bonding the first contact to the second contact by melting the interlayer to diffuse the interlayer into the first and second contacts. The bonded first and second contacts have a higher melting temperature than the interlayer before melting. In other example embodiments, an electronic assembly includes a motherboard having a first contact that is bonded to a second contact on an electronic package. An interlayer is diffused within the first and second contacts such that they have a higher melting temperature than the interlayer before the interlayer is diffused into the first and second contacts.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventor: Daewoong Suh
  • Patent number: 7700476
    Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Stephen E. Lehman, Jr., Mukul Renavikar
  • Publication number: 20100065246
    Abstract: Methods and associated structures of forming an indium containing solder material directly on an active region of a copper HIS is enabled. A copper indium containing solder intermetallic is formed on the active region of the IHS. The solder intermetallic improves the solder-TIM integration process for microelectronic packaging applications.
    Type: Application
    Filed: September 17, 2008
    Publication date: March 18, 2010
    Inventors: Abhishek Gupta, Mike Boyd, Carl Deppisch, Jinlin Wang, Daewoong Suh, Brad Drew
  • Publication number: 20100044848
    Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.
    Type: Application
    Filed: October 30, 2009
    Publication date: February 25, 2010
    Inventors: Daewoong Suh, Stephen E. Lehman, JR., Mukul Renavikar
  • Patent number: 7666768
    Abstract: A method, apparatus and various material-architectures in an electrically conductive through die via formed of a composite material with a continuous phase of matrix metal and a dispersed phase of graphitic structures of carbon, wherein bulk material properties of the composite material differ from similar bulk material properties of the matrix metal.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: February 23, 2010
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, Daewoong Suh, Leonel Arana, James C. Matayabas, Jr.
  • Publication number: 20100037990
    Abstract: High strength, reliable bulk metallic glass (BMG) solder materials formed from alloys possessing deep eutectics with asymmetric liquidous slopes. BMG solder materials are stronger and have a higher elastic modulus than, and therefore are less likely than crystalline solder materials to damage fragile low k interlayer dielectric (ILD) materials due to thermal stress in materials with different coefficients of thermal expansion (CTE). BMG solder materials may physically, electrically, or thermally couple a feature to another feature, or any combination thereof. For example, in an embodiment of the invention, a BMG solder material may physically and electrically couple an electronic component to a printed circuit board. In another embodiment of the invention, a BMG solder material may physically and thermally couple an integrated heat sink to a semiconductor device.
    Type: Application
    Filed: October 26, 2009
    Publication date: February 18, 2010
    Inventor: Daewoong Suh
  • Publication number: 20100039777
    Abstract: A microelectronic package is provided. The microelectronic package includes a substrate, a die coupled to a top surface of the substrate and a integrated heat spreader thermally coupled to the die, wherein the integrated heat spreader comprises integrated heat spreader walls. The microelectronic package also includes a thermal interface material disposed between the die and the integrated heat spreader and an underfill material disposed between the integrated heat spreader and the substrate, wherein the underfill material is disposed within gaps between the integrated heat spreader walls, the die and the thermal interface material.
    Type: Application
    Filed: August 15, 2008
    Publication date: February 18, 2010
    Inventors: Sabina Houle, Daewoong Suh, Charles Hill
  • Publication number: 20090321962
    Abstract: A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate and a die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventor: Daewoong Suh
  • Patent number: 7628871
    Abstract: High strength, reliable bulk metallic glass (BMG) solder materials formed from alloys possessing deep eutectics with asymmetric liquidous slopes. BMG solder materials are stronger and have a higher elastic modulus than, and therefore are less likely than crystalline solder materials to damage fragile low k interlayer dielectric (ILD) materials due to thermal stress in materials with different coefficients of thermal expansion (CTE). BMG solder materials may physically, electrically, or thermally couple a feature to another feature, or any combination thereof. For example, in an embodiment of the invention, a BMG solder material may physically and electrically couple an electronic component to a printed circuit board. In another embodiment of the invention, a BMG solder material may physically and thermally couple an integrated heat sink to a semiconductor device.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: December 8, 2009
    Assignee: Intel Corporation
    Inventor: Daewoong Suh
  • Patent number: 7629203
    Abstract: A combined thermal interface material and second layer interconnect reflow material and method are disclosed.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: December 8, 2009
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Sabina Houle, Edward A Zarbock
  • Publication number: 20090244850
    Abstract: A combined thermal interface material and second layer interconnect reflow material and method are disclosed.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Daewoong Suh, Sabina Houle, Edward A. Zarbock
  • Publication number: 20090242121
    Abstract: In some embodiments, a low stress, low-temperature metal-metal composite flip chip interconnect is presented. In this regard, a method is introduced consisting of combining a powder of substantially pure tin with a powder of tin alloy having a lower melting point than pure tin and depositing the combination of metals between an integrated circuit device and a package substrate. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventor: Daewoong Suh
  • Patent number: 7578966
    Abstract: A solder composition includes a reflow-wetting element that is an intermetallic both pre-reflow and post-reflow. The intermetallic releases the reflow-wetting element upon heating. The solder composition includes the intermetallic first phase in a bulk-solder second phase. A method of assembling a microelectronic package includes the intermetallic in a solder. A computing system also includes the intermetallic first phase in the bulk-solder second phase.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: August 25, 2009
    Assignee: Intel Corporation
    Inventor: Daewoong Suh
  • Publication number: 20090128274
    Abstract: Inductors using bulk metallic glass (BMG) material and associated methods are generally described. In one example, an apparatus includes an electrically conductive core material, an electrically insulative material coupled with the electrically conductive core material, and a magnetic bulk metallic glass (BMG) material coupled with the electrically insulative material, wherein the electrically conductive core material, the electrically insulative material, and the magnetic BMG material form an inductor.
    Type: Application
    Filed: November 20, 2007
    Publication date: May 21, 2009
    Inventors: Chang-min Park, Daewoong Suh
  • Patent number: 7535099
    Abstract: A microelectronic cooling assembly and method for fabricating the same are described. In one example, a microelectronic cooling assembly includes a microelectronic device, a heat spreader, and a thermal interface material (TIM) that thermally joins the microelectronic device and heat spreader, the TIM comprising a sintered metallic nanopaste.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Chi-won Hwang