Patents by Inventor Daisuke Arai

Daisuke Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200076290
    Abstract: A power conversion circuit includes: a MOSFET having a super junction structure; an inductive load; and a freewheel diode. A switching frequency of the MOSFET is 10 kHz or more. When the MOSFET is turned off, a first period during which a drain current decreases, a second period during which the drain current increases, and a third period during which the drain current decreases again appear in this order. The freewheel diode is an Si-FRD or an SiC-SBD, and current density obtained by dividing a current value of the forward current by an area of an active region of the freewheel diode falls within a range of 200 A/cm2 to 400 A/cm2 when the freewheel diode is the Si-FRD, and the current density falls within a range of 400 A/cm2 to 1500 A/cm2 when the freewheel diode is the SiC-SBD.
    Type: Application
    Filed: November 17, 2017
    Publication date: March 5, 2020
    Inventors: Daisuke ARAI, Shigeru HISADA, Mizue KITADA
  • Publication number: 20200020536
    Abstract: A MOSFET includes: a semiconductor base substrate having n-type column regions and p-type column regions, the n-type column regions and the p-type column regions forming a super junction structure; and a gate electrode which is formed on a first main surface side of the semiconductor base substrate by way of a gate insulation film, wherein crystal defects whose density is increased locally as viewed along a depth direction are formed in the n-type column regions and the p-type column regions, using the first main surface as a reference and assuming a depth to a deepest portion of the super junction structure as Dp, a depth at which density of the crystal defects exhibits a maximum value as Dd, and a half value width of density distribution of the crystal defects as W, a relationship of 0.25Dp?Dd<0.95Dp and a relationship of 0.05Dp<W<0.5Dp are satisfied.
    Type: Application
    Filed: July 26, 2019
    Publication date: January 16, 2020
    Inventors: Daisuke ARAI, Mizue KITADA, Takeshi ASADA, Noriaki SUZUKI, Koichi Murakami
  • Publication number: 20200002514
    Abstract: A golf ball includes a core and a cover. The core is formed of a material molded under heat from a rubber composition. The rubber composition includes components (A) through (C). The components (A) through (C) are (A) a base rubber, (B) an organic peroxide, and (C) a water providing agent. The water providing agent releases water at a vulcanization temperature at which the rubber composition is vulcanized. The dissociation rate of water of the water providing agent in the case of heating the water providing agent up to the vulcanization temperature of the rubber composition is 60% by mass or more.
    Type: Application
    Filed: April 15, 2019
    Publication date: January 2, 2020
    Inventors: Eiji YAMANAKA, Daisuke ARAI
  • Publication number: 20200001143
    Abstract: A rubber composition for golf balls includes (a) a base rubber, (b) a co-crosslinking agent which is an ?,?-unsaturated carboxylic acid and/or a metal salt thereof, (c) an organic peroxide, (d) water or an alcohol, and (e) an antioxidant which is a benzoimidazole of the following general formula and/or a metal salt thereof. When the rubber composition is used in constituent members of a golf ball, especially the core, the golf ball exhibits low spin properties on shots, resulting in an improved flight performance and enabling a good durability to be maintained.
    Type: Application
    Filed: June 21, 2019
    Publication date: January 2, 2020
    Applicant: BRIDGESTONE SPORTS CO., LTD
    Inventors: Jun SHINDO, Daisuke ARAI
  • Publication number: 20200001142
    Abstract: A golf ball includes a core and a cover. The core is formed of a material molded under heat from a rubber composition. The rubber composition includes components (A) through (C). The components (A) through (C) are (A) a base rubber, (B) an organic peroxide, and (C) a metal salt containing hydration water.
    Type: Application
    Filed: April 15, 2019
    Publication date: January 2, 2020
    Inventors: Eiji YAMANAKA, Daisuke ARAI
  • Patent number: 10475917
    Abstract: A MOSFET includes a semiconductor base substrate where a super junction structure is formed of an n-type column region and a p-type column region. A total amount of a dopant in the n-type column region is set to a value greater than a total amount of a dopant in the p-type column region. The MOSFET is configured to be operated during a period from a point of time when a drain current starts to decrease to a point of time when the drain current becomes 0 for the first time in response to turning off of the MOSFET such that a first period during which the drain current is decreased, a second period during which the drain current is increased or the drain current becomes constant, and a third period during which the drain current is decreased again occur in this order.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: November 12, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Daisuke Arai, Shigeru Hisada, Mizue Kitada, Takeshi Asada
  • Patent number: 10468518
    Abstract: A power semiconductor device of the present invention includes: a semiconductor base body which has a super junction structure formed of a plurality of first conductive-type columnar regions and a plurality of second conductive-type columnar regions; a plurality of trenches; gate insulation films; gate electrodes; an interlayer insulation film; contact holes formed such that two or more contact holes are formed between two trenches disposed adjacently to each other; metal plugs formed by filling the inside of the contact holes with metal; and an electrode, wherein a first conductive-type high concentration diffusion region is formed only between the trench and the metal plug disposed closest to the trench between each two trenches disposed adjacently to each other. According to the power semiconductor device of the present invention, it is possible to provide a power semiconductor device which satisfies a demand for reduction in cost and downsizing of electronic equipment, and has a large breakdown strength.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: November 5, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Mizue Kitada, Takeshi Asada, Takeshi Yamaguchi, Noriaki Suzuki, Daisuke Arai
  • Patent number: 10468480
    Abstract: Provided is a MOSFET which includes: a semiconductor base substrate having an n-type column region and a p-type column region, a base region and a source region, wherein a super junction structure is formed of the n-type column region and the p-type column region; a trench having side walls and a bottom; a gate electrode formed in the trench by way of a gate insulation film; a carrier compensation electrode positioned between the gate electrode and the bottom of the trench; an insulation region separating the carrier compensation electrode from the side walls and the bottom; and a source electrode electrically connected to the source region and also electrically connected to the carrier compensation electrode. According to the MOSFET of the present invention, even when an irregularity in a charge balance occurs around the gate, an irregularity in switching characteristics when the MOSFET is turned off can be decreased.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: November 5, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Daisuke Arai, Mizue Kitada
  • Publication number: 20190326388
    Abstract: Provided is a MOSFET which includes: a semiconductor base substrate having an n-type column region and a p-type column region, a base region and a source region, wherein a super junction structure is formed of the n-type column region and the p-type column region; a trench having side walls and a bottom; a gate electrode formed in the trench by way of a gate insulation film; a carrier compensation electrode positioned between the gate electrode and the bottom of the trench; an insulation region separating the carrier compensation electrode from the side walls and the bottom; and a source electrode electrically connected to the source region and also electrically connected to the carrier compensation electrode. According to the MOSFET of the present invention, even when an irregularity in a charge balance occurs around the gate, an irregularity in switching characteristics when the MOSFET is turned off can be decreased.
    Type: Application
    Filed: November 11, 2016
    Publication date: October 24, 2019
    Inventors: Daisuke ARAI, Mizue KITADA
  • Patent number: 10453661
    Abstract: An ion filter is used for a gas detector including a gas electron multiplier. The ion filter includes: an insulating substrate; a first patterned conductive layer on one main surface of the insulating substrate; and a second patterned conductive layer on another main surface of the insulating substrate. The ion filter has a plurality of through-holes formed along a thickness direction of the insulating substrate on which the first patterned conductive layer and the second patterned conductive layer are formed. The one main surface of the insulating substrate is disposed on an upstream side in a movement direction of electrons in the gas detector. The other main surface of the insulating substrate is disposed on a downstream side in the movement direction of the electrons in the gas detector. The first patterned conductive layer has a line width thicker than a line width of the second patterned conductive layer.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: October 22, 2019
    Assignee: FUJIKURA LTD.
    Inventor: Daisuke Arai
  • Patent number: 10439056
    Abstract: A power semiconductor device according to the present invention has a super junction structure, and includes a low-resistance semiconductor layer, an n?-type column region, p?-type column regions, a base region, trenches, gate insulation films, gate electrodes, source regions, interlayer insulation films, contact holes, metal plugs, p+-type diffusion regions, a source electrode and a gate pad electrode. An active element part includes an n?-type column region between a predetermined p?-type column region disposed closest to a gate pad part and a predetermined n?-type column region disposed closest to the gate pad part among the n?-type column regions which are in contact with the trenches. The present invention provides a power semiconductor device which can satisfy a demand for reduction in cost and downsizing of electronic equipment, can lower ON resistance while maintaining a high withstand voltage, and can possess a large breakdown resistance.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: October 8, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Daisuke Arai, Mizue Kitada, Takeshi Asada, Takeshi Yamaguchi, Noriaki Suzuki
  • Patent number: 10411141
    Abstract: A semiconductor device includes: a semiconductor base body where a second semiconductor layer is stacked on a first semiconductor layer, a trench is formed on a surface of the second semiconductor layer, and a third semiconductor layer which is formed of an epitaxial layer is formed in the inside of the trench; a first electrode; an interlayer insulation film which has a predetermined opening; and a second electrode, wherein metal is filled in the opening, the opening is disposed at a position avoiding a center portion of the third semiconductor layer, the second electrode is connected to the third semiconductor layer through the metal, and a surface of the center portion of the third semiconductor layer is covered by the interlayer insulation film.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 10, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Mizue Kitada, Takeshi Asada, Takeshi Yamaguchi, Noriaki Suzuki, Daisuke Arai
  • Patent number: 10388923
    Abstract: In a vehicle battery unit, since a second support plate (30B) and a second end plate (29B) of a second battery module (22B) having a plurality of battery cells (21) stacked are placed on top of a first support plate (30A) and a first end plate (29A) of a first battery module (22A) having a plurality of the battery cells (21), it is possible to prevent the weight of the second battery module (22B) from being imposed on the battery cells (21) of the first battery module (22A). Moreover, since it is not necessary to provide on the exterior of the first battery module (22A) a member for supporting the weight of the second battery module (22B), it is possible to reduce the dimensions of the first battery module (22A).
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: August 20, 2019
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Koichi Takahashi, Eiji Koike, Daisuke Arai, Takurou Kamada, Kentaro Shibuya, Harumi Takedomi
  • Patent number: 10365679
    Abstract: A regenerative current detection circuit includes a first power MOS transistor that is configured as a current mirror to a second power MOS transistor connected to drive a motor winding, a first feedback amplifier that compares a first regenerative current that flows in the first power MOS transistor with a second regenerative current that flows in the second power MOS transistor and outputs a comparison result, the first regenerative current being obtained by multiplying the second regenerative current by a current mirror ratio, and a current detection circuit that outputs a detection current based on the comparison result.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 30, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daisuke Arai, Tooru Asakawa, Masahiro Shimozono, Katsumi Shiokawa
  • Publication number: 20190221664
    Abstract: A MOSFET used in a power conversion circuit having a reactor, a power source, the MOSFET, and a rectifier element, includes a semiconductor base substrate with a super junction structure formed of an n-type column region and a p-type column region. A total amount of a dopant in the n-type column region is higher than a total amount of a dopant in the p-type column region. The MOSFET is configured to be operated during a period from a point of time when a drain current starts to decrease to a point of time when the drain current becomes 0 for the first time in response to turning off of the MOSFET such that a first period during which the drain current decreases, a second period during which the drain current increases, and a third period during which the drain current decreases again appear in this order.
    Type: Application
    Filed: September 2, 2016
    Publication date: July 18, 2019
    Inventors: Daisuke ARAI, Shigeru HISADA, Mizue KITADA, Takeshi ASADA
  • Publication number: 20190214496
    Abstract: A MOSFET used in a power conversion circuit including a reactor, a power source, the MOSFET, and a rectifier element, includes a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure, the n-type column region and the p-type column region are formed such that a total amount of a dopant in the p-type column region is set higher than a total amount of a dopant in the n-type column region, and the MOSFET is configured to be operated in response to turning on of the MOSFET such that at a center of the n-type column region as viewed in a plan view, a low electric field region having lower field intensity than areas of the n-type column region other than the center of the n-type column region appears.
    Type: Application
    Filed: September 16, 2016
    Publication date: July 11, 2019
    Inventors: Daisuke ARAI, Shigeru HISADA, Mizue KITADA, Takeshi ASADA
  • Publication number: 20190161298
    Abstract: A sheet conveying device, which is included in an image forming apparatus, includes a pair of rotary bodies configured to convey a sheet and correct a positional deviation of the sheet, a pair of downstream side sheet conveying bodies disposed downstream from the pair of rotary bodies in a sheet conveying direction and configured to convey the sheet, and a detector configured to detect separation of the pair of rotary bodies. The pair of rotary bodies moves the sheet by moving from a home position on a sheet conveyance passage through which the sheet passes. The pair of rotary bodies moves to the home position while the pair of downstream side sheet conveying bodies is conveying the sheet, in response to detection of the separation of the pair of rotary bodies by the detector.
    Type: Application
    Filed: September 25, 2018
    Publication date: May 30, 2019
    Applicant: Ricoh Company, Ltd.
    Inventors: Daisuke ARAI, Takehiro FUJITA
  • Publication number: 20190165161
    Abstract: A MOSFET includes a semiconductor base substrate where a super junction structure is formed of an n-type column region and a p-type column region. A total amount of a dopant in the n-type column region is set to a value greater than a total amount of a dopant in the p-type column region. The MOSFET is configured to be operated during a period from a point of time when a drain current starts to decrease to a point of time when the drain current becomes 0 for the first time in response to turning off of the MOSFET such that a first period during which the drain current is decreased, a second period during which the drain current is increased or the drain current becomes constant, and a third period during which the drain current is decreased again occur in this order.
    Type: Application
    Filed: May 21, 2018
    Publication date: May 30, 2019
    Inventors: Daisuke ARAI, Shigeru HISADA, Mizue KITADA, Takeshi ASADA
  • Patent number: 10290734
    Abstract: A MOSFET includes: a semiconductor base substrate having a super junction structure; and a gate electrode formed on a first main surface side of the semiconductor base substrate by way of a gate insulation film. In a graph where a depth x at a predetermined depth position in the super junction structure is taken on an axis of abscissas, and an average positive charge density ?(x) at the predetermined depth position in the super junction structure is taken on an axis of ordinates, the average positive charge density ?(x) at a predetermined depth position of the super junction structure when the super junction structure is depleted by turning off the MOSFET is expressed by an upward convex curve projecting in a right upward direction.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: May 14, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Daisuke Arai, Mizue Kitada
  • Publication number: 20190081172
    Abstract: A MOSFET includes: a semiconductor base substrate having a super junction structure; and a gate electrode formed on a first main surface side of the semiconductor base substrate by way of a gate insulation film. In a graph where a depth x at a predetermined depth position in the super junction structure is taken on an axis of abscissas, and an average positive charge density ?(x) at the predetermined depth position in the super junction structure is taken on an axis of ordinates, the average positive charge density ?(x) at a predetermined depth position of the super junction structure when the super junction structure is depleted by turning off the MOSFET is expressed by an upward convex curve projecting in a right upward direction.
    Type: Application
    Filed: March 17, 2017
    Publication date: March 14, 2019
    Inventors: Daisuke ARAI, Mizue KITADA