Patents by Inventor Daisuke Matsushita

Daisuke Matsushita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070018231
    Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.
    Type: Application
    Filed: July 24, 2006
    Publication date: January 25, 2007
    Inventors: Yuuichiro Mitani, Daisuke Matsushita, Ryuji Ooba, Isao Kamioka, Yoshio Ozawa
  • Publication number: 20060278940
    Abstract: A semiconductor device includes a semiconductor substrate; an insulation film provided on the semiconductor substrate; and an electrode provided on the insulation film, and containing boron and a semiconductor material, wherein at least one element of the group V and carbon is introduced into an interface between the insulation film and the electrode.
    Type: Application
    Filed: November 28, 2005
    Publication date: December 14, 2006
    Inventors: Koichi Kato, Daisuke Matsushita, Koichi Muraoka, Yasushi Nakasaki, Yuichiro Mitani, Nobutoshi Aoki
  • Publication number: 20060237837
    Abstract: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a convex channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.
    Type: Application
    Filed: June 22, 2006
    Publication date: October 26, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yukie Nishikawa, Hideki Satake, Noburu Fukushima
  • Patent number: 7091561
    Abstract: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a convex channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: August 15, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yukie Nishikawa, Hideki Satake, Noburu Fukushima
  • Publication number: 20060175672
    Abstract: According to an aspect of the present invention, there is disclosed a semiconductor device comprising a semiconductor substrate, and a gate insulating film of a P-channel MOS transistor, formed on the semiconductor substrate. The gate insulating film has an oxide film (SiO2), and a diffusion preventive film (BN) containing boron and nitrogen atoms.
    Type: Application
    Filed: August 5, 2005
    Publication date: August 10, 2006
    Inventors: Daisuke Matsushita, Koichi Muraoka, Yasushi Nakasaki, Koichi Kato, Takashi Shimizu
  • Publication number: 20060054961
    Abstract: A semiconductor device includes a silicon substrate; an insulation layer formed on the silicon substrate, the insulation layer containing an oxide of an element of at least one kind selected from at least Hf, Zr, Ti and Ta; an electrode formed on the insulation layer; and a metal oxide layer containing La and Al, the metal oxide layer being provided at at least one of an interface between the silicon substrate and the insulation layer and an interface between the insulation layer and the electrode.
    Type: Application
    Filed: July 8, 2005
    Publication date: March 16, 2006
    Inventors: Masamichi Suzuki, Daisuke Matsushita, Takeshi Yamaguchi
  • Publication number: 20050285180
    Abstract: A nonvolatile semiconductor memory device includes a floating gate electrode which is selectively formed on a main surface of a first conductivity type with a first gate insulating film interposed therebetween, a control gate electrode formed on the floating gate electrode with a second gate insulating film interposed therebetween, and source/drain regions of a second conductivity type which are formed in the main surface of the substrate in correspondence with the respective gate electrodes. The first gate electrode has a three-layer structure in which a silicon nitride film is held between silicon oxide films, and the silicon nitride film includes triple coordinate nitrogen bonds.
    Type: Application
    Filed: March 18, 2005
    Publication date: December 29, 2005
    Inventors: Yuichiro Mitani, Daisuke Matsushita
  • Publication number: 20050064667
    Abstract: A semiconductor device manufacturing method comprises: forming a first nitride film on a semiconductor substrate; forming a first oxide film between said semiconductor substrate and said nitride film and forming a second oxide film on said nitride film; forming a second nitride film or an oxide and nitride film on said first nitride film by nitriding said second oxide film; and forming a gate electrode on a gate insulative film including said first oxide film, said first nitride film, and said second nitride film or said oxide and nitride film.
    Type: Application
    Filed: September 16, 2004
    Publication date: March 24, 2005
    Inventors: Daisuke Matsushita, Koichi Muraoka, Seiji Inumiya, Koichi Kato, Kazuhiro Eguchi, Mariko Takayanagi, Yasushi Nakasaki
  • Publication number: 20050017304
    Abstract: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a convex channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.
    Type: Application
    Filed: June 9, 2004
    Publication date: January 27, 2005
    Inventors: Daisuke Matsushita, Yukie Nishikawa, Hideki Satake, Noburu Fukushima