Patents by Inventor Daisuke Matsushita

Daisuke Matsushita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7863119
    Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: January 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yuuichiro Mitani
  • Patent number: 7833865
    Abstract: A semiconductor device includes a silicon substrate; an insulation layer formed on the silicon substrate, the insulation layer containing an oxide of an element of at least one kind selected from at least Hf, Zr, Ti and Ta; an electrode formed on the insulation layer; and a metal oxide layer containing La and Al, the metal oxide layer being provided at at least one of an interface between the silicon substrate and the insulation layer and an interface between the insulation layer and the electrode.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: November 16, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamichi Suzuki, Daisuke Matsushita, Takeshi Yamaguchi
  • Patent number: 7816215
    Abstract: A semiconductor device manufacturing method comprises: forming a gate insulative film on a semiconductor substrate by: forming a first nitride film on the substrate; forming a first oxide film and a second oxide film, the first oxide film being between the substrate and the first nitride film, the second oxide film being on the first nitride film; and nitriding the second oxide film to form, on the first nitride film, one of either: a second nitride film or an SiON film; and forming a gate electrode on the gate insulative film; wherein the equivalent oxide thickness of the gate insulative film is equal to or less than 1 nm.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: October 19, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Koichi Muraoka, Seiji Inumiya, Koichi Kato, Kazuhiro Eguchi, Mariko Takayanagi, Yasushi Nakasaki
  • Patent number: 7772129
    Abstract: It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: August 10, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Koichi Muraoka, Koichi Kato, Yasushi Nakasaki, Yuichiro Mitani
  • Publication number: 20100171169
    Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.
    Type: Application
    Filed: March 17, 2010
    Publication date: July 8, 2010
    Inventors: Yuuichiro Mitani, Daisuke Matsushita, Ryuji Ooba, Isao Kamioka, Yoshio Ozawa
  • Patent number: 7749919
    Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: July 6, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiwamu Sakuma, Daisuke Matsushita, Koichi Kato, Yasushi Nakasaki, Izumi Hirano, Kouichi Muraoka, Yuichiro Mitani, Shigeto Fukatsu, Toshihide Ito
  • Publication number: 20100078704
    Abstract: A semiconductor storage element includes: a source region and a drain region provided in a semiconductor substrate; a tunnel insulating film provided on the semiconductor substrate between the source region and the drain region; a charge storage film provided on the tunnel insulating film; a block insulating film provided on the charge storage film; a gate electrode provided on the block insulating film; and a region containing a gas molecule, the region provided in a neighborhood of an interface between the charge storage film and the block insulating film.
    Type: Application
    Filed: March 16, 2009
    Publication date: April 1, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsunehiro Ino, Shosuke Fujii, Jun Fujiki, Akira Takashima, Masao Shingu, Daisuke Matsushita, Naoki Yasuda, Koichi Muraoka
  • Publication number: 20100052039
    Abstract: A semiconductor device of an embodiment can prevent nitriding of the lower-layer insulating film and oxygen diffusion from the upper-layer insulating film, so as to minimize the decrease in charge capture density. This semiconductor device includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a nitrogen-added amorphous silicon layer formed on the first insulating film, a first silicon nitride layer formed on the amorphous silicon layer, and a second insulating film formed above the first silicon nitride layer.
    Type: Application
    Filed: July 23, 2009
    Publication date: March 4, 2010
    Inventors: Daisuke MATSUSHITA, Yuichiro MITANI
  • Publication number: 20100041193
    Abstract: A nonvolatile semiconductor memory device includes a floating gate electrode which is selectively formed on a main surface of a first conductivity type with a first gate insulating film interposed therebetween, a control gate electrode formed on the floating gate electrode with a second gate insulating film interposed therebetween, and source/drain regions of a second conductivity type which are formed in the main surface of the substrate in correspondence with the respective gate electrodes. The first gate electrode has a three-layer structure in which a silicon nitride film is held between silicon oxide films, and the silicon nitride film includes triple coordinate nitrogen bonds.
    Type: Application
    Filed: October 23, 2009
    Publication date: February 18, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Daisuke Matsushita
  • Patent number: 7619274
    Abstract: A nonvolatile semiconductor memory device includes a floating gate electrode which is selectively formed on a main surface of a first conductivity type with a first gate insulating film interposed therebetween, a control gate electrode formed on the floating gate electrode with a second gate insulating film interposed therebetween, and source/drain regions of a second conductivity type which are formed in the main surface of the substrate in correspondence with the respective gate electrodes. The first gate electrode has a three-layer structure in which a silicon nitride film is held between silicon oxide films, and the silicon nitride film includes triple coordinate nitrogen bonds.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: November 17, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Daisuke Matsushita
  • Patent number: 7586163
    Abstract: A semiconductor device includes a semiconductor substrate; an insulation film provided on the semiconductor substrate; and an electrode provided on the insulation film, and containing boron and a semiconductor material, wherein at least one element of the group V and carbon is introduced into an interface between the insulation film and the electrode.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: September 8, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Kato, Daisuke Matsushita, Koichi Muraoka, Yasushi Nakasaki, Yuichiro Mitani, Nobutoshi Aoki
  • Publication number: 20090184401
    Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.
    Type: Application
    Filed: August 28, 2008
    Publication date: July 23, 2009
    Inventors: Daisuke MATSUSHITA, Yuuichiro Mitani
  • Patent number: 7538013
    Abstract: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: May 26, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yukie Nishikawa, Hideki Satake, Noburu Fukushima
  • Publication number: 20080318404
    Abstract: A semiconductor device includes a silicon substrate; an insulation layer formed on the silicon substrate, the insulation layer containing an oxide of an element of at least one kind selected from at least Hf, Zr, Ti and Ta; an electrode formed on the insulation layer; and a metal oxide layer containing La and Al, the metal oxide layer being provided at at least one of an interface between the silicon substrate and the insulation layer and an interface between the insulation layer and the electrode.
    Type: Application
    Filed: May 5, 2008
    Publication date: December 25, 2008
    Inventors: Masamichi Suzuki, Daisuke Matsushita, Takeshi Yamaguchi
  • Publication number: 20080305647
    Abstract: It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.
    Type: Application
    Filed: August 28, 2006
    Publication date: December 11, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daisuke Matsushita, Koichi Muraoka, Koichi Kato, Yasushi Nakasaki, Yuichiro Mitani
  • Publication number: 20080173927
    Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.
    Type: Application
    Filed: September 6, 2007
    Publication date: July 24, 2008
    Inventors: Kiwamu Sakuma, Daisuke Matsushita, Koichi Kato, Yasushi Nakasaki, Izumi Hirano, Kouichi Muraoka, Yuichiro Mitani, Shigeto Fukatsu, Toshihide Ito
  • Publication number: 20080173930
    Abstract: The present invention provides a semiconductor memory device having a tunnel insulating film that does not degrade the endurance characteristics when writing/erasing is repeated, even if the tunnel insulating film is made thinner. The semiconductor memory device includes: a semiconductor substrate; a first insulating film formed on the semiconductor substrate, and including a silicon oxynitride film and a silicon-rich silicon oxide film formed on the silicon oxynitride film, the silicon oxynitride film having a stacked structure formed with a first silicon oxynitride layer, a silicon nitride layer, and a second silicon oxynitride layer in order; a charge storage layer formed on the first insulating film; a second insulating film formed on the charge storage layer; and a control gate formed on the second insulating film.
    Type: Application
    Filed: September 19, 2007
    Publication date: July 24, 2008
    Inventors: Hiroshi Watanabe, Daisuke Matsushita, Kouichi Muraoka, Yasushi Nakasaki, Koichi Kato
  • Publication number: 20080135922
    Abstract: A nonvolatile semiconductor memory device includes: a memory element, the memory element including: a semiconductor substrate; a first insulating film formed on a region in the semiconductor substrate located between a source region and a drain region, and having a stack structure formed with a first insulating layer, a second insulating layer, and a third insulating layer in this order, the first insulating layer including an electron trapping site, the second insulating layer not including the electron trapping site, and the third insulating layer including the electron trapping site, and the electron trapping site being located in a position lower than conduction band minimum of the first through third insulating layers while being located in a position higher than conduction band minimum of a material forming the semiconductor substrate; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second i
    Type: Application
    Filed: September 13, 2007
    Publication date: June 12, 2008
    Inventors: Yuichiro Mitani, Masahiro Koike, Yasushi Nakasaki, Daisuke Matsushita
  • Publication number: 20070222003
    Abstract: According to an aspect of the present invention, there is disclosed a semiconductor device comprising a semiconductor substrate, and a gate insulating film of a P-channel MOS transistor, formed on the semiconductor substrate. The gate insulating film has an oxide film (SiO2), and a diffusion preventive film (BN) containing boron and nitrogen atoms.
    Type: Application
    Filed: May 24, 2007
    Publication date: September 27, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Koichi Muraoka, Yasushi Nakasaki, Koichi Kato, Takashi Shimizu
  • Patent number: 7238997
    Abstract: According to an aspect of the present invention, there is disclosed a semiconductor device comprising a semiconductor substrate, and a gate insulating film of a P-channel MOS transistor, formed on the semiconductor substrate. The gate insulating film has an oxide film (SiO2), and a diffusion preventive film (BN) containing boron and nitrogen atoms.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: July 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Koichi Muraoka, Yasushi Nakasaki, Koichi Kato, Takashi Shimizu