Patents by Inventor Daisuke Matsushita

Daisuke Matsushita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120319074
    Abstract: According to one embodiment, a resistance change device includes a first electrode including a metal, a second electrode, and an amorphous oxide layer including Si and O between the first and second electrode, the layer having a concentration gradient of O and a first peak thereof in a direction from the first electrode to the second electrode.
    Type: Application
    Filed: August 29, 2012
    Publication date: December 20, 2012
    Inventors: Shosuke FUJII, Daisuke Matsushita, Yuichiro Mitani
  • Publication number: 20120292685
    Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.
    Type: Application
    Filed: July 27, 2012
    Publication date: November 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yuuichiro Mitani
  • Publication number: 20120243292
    Abstract: According to one embodiment, a memory device includes a first electrode including a crystallized SixGe1-x layer (0?x<1), a second electrode including a metal element, a variable resistance part between the first and second electrode, the part including an amorphous Si layer, and a control circuit controlling a filament in the amorphous Si layer, the filament including the metal element.
    Type: Application
    Filed: September 16, 2011
    Publication date: September 27, 2012
    Inventors: Akira TAKASHIMA, Daisuke Matsushita, Takashi Yamauchi, Yuuichi Kamimuta, Hidenori Miyagawa
  • Publication number: 20120235223
    Abstract: According to one embodiment, a nonvolatile semiconductor memory including a first gate insulating film formed on a channel region of a semiconductor substrate, a first particle layer formed in the first gate insulating film, a charge storage part formed on the first gate insulating film, a second gate insulating film which is formed on the charge storage part, a second particle layer formed in the second gate insulating film, and a gate electrode formed on the second gate insulating film. The first particle layer includes first conductive particles that satisfy Coulomb blockade conditions. The second particle layer includes second conductive particles that satisfy Coulomb blockade conditions and differs from the first conductive particles in average particle diameter.
    Type: Application
    Filed: March 22, 2012
    Publication date: September 20, 2012
    Inventors: Ryuji OHBA, Daisuke Matsushita
  • Patent number: 8253190
    Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: August 28, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yuuichiro Mitani
  • Patent number: 8211811
    Abstract: A semiconductor device of an embodiment can prevent nitriding of the lower-layer insulating film and oxygen diffusion from the upper-layer insulating film, so as to minimize the decrease in charge capture density. This semiconductor device includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a nitrogen-added amorphous silicon layer formed on the first insulating film, a first silicon nitride layer formed on the amorphous silicon layer, and a second insulating film formed above the first silicon nitride layer.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: July 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yuichiro Mitani
  • Publication number: 20120142180
    Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes: forming a stack structure by alternately stacking control gate electrodes and interlayer insulating films; forming a through-hole that penetrates through the stack structure in a stacking direction of the control gate electrodes and the interlayer insulating films; forming a first insulating film that covers an inner surface of the through-hole; forming a charge storage layer that covers an inner surface of the first insulating film; forming a second insulating film that covers an inner surface of the charge storage layer; forming a semiconductor layer that covers an inner surface of the second insulating film; and oxidizing an interface between the semiconductor layer and the second insulating film by performing a heat treatment in an atmosphere containing O2 gas at a temperature of 600° C. or lower.
    Type: Application
    Filed: February 10, 2012
    Publication date: June 7, 2012
    Inventors: Daisuke MATSUSHITA, Koichi KATO, Yuichiro MITAINI
  • Publication number: 20120068250
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor region, a tunnel insulating film provided on the semiconductor region, a charge storage insulating film provided on the tunnel insulating film and having a hafnium oxide including a cubic region, a block insulating film provided on the charge storage insulating film, and a control gate electrode provided on the block insulating film.
    Type: Application
    Filed: September 19, 2011
    Publication date: March 22, 2012
    Inventors: Tsunehiro Ino, Masao Shingu, Shosuke Fujii, Akira Takashima, Daisuke Matsushita, Jun Fujiki, Naoki Yasuda, Yasushi Nakasaki, Koichi Muraoka
  • Publication number: 20120068159
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first memory portion. The first memory portion includes a first base semiconductor layer, a first electrode, a first channel semiconductor layer, a first base tunnel insulating film, a first channel tunnel insulating, a first charge retention layer and a first block insulating film. The first channel semiconductor layer is provided between the first base semiconductor layer and the first electrode, and includes a first channel portion. The first base tunnel insulating film is provided between the first base semiconductor layer and the first channel semiconductor layer. The first channel tunnel insulating film is provided between the first electrode and the first channel portion. The first charge retention layer is provided between the first electrode and the first channel tunnel insulating film. The first block insulating film is provided between the first electrode and the first charge retention layer.
    Type: Application
    Filed: March 23, 2011
    Publication date: March 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jun FUJIKI, Naoki Yasuda, Daisuke Matsushita
  • Publication number: 20120018792
    Abstract: A method of manufacturing a nonvolatile semiconductor memory device according to an embodiment, includes: forming a first insulating film on a semiconductor substrate; forming a charge trapping film on the first insulating film, the forming of the charge trapping film including; forming a first nitride layer on the first insulating film at a heat treatment temperature of 550° C. or higher, forming a first oxynitride layer on the first nitride layer by oxidizing a surface of the first nitride layer, and forming a second nitride layer on the first oxynitride layer; forming a second insulating film on the charge trapping film; and forming a control gate on the second insulating film.
    Type: Application
    Filed: January 21, 2010
    Publication date: January 26, 2012
    Inventors: Daisuke Matsushita, Ryuji Ohba, Yuichiro Mitani
  • Publication number: 20120012917
    Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.
    Type: Application
    Filed: September 21, 2011
    Publication date: January 19, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yuuichiro Mitani
  • Patent number: 8093126
    Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: January 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuuichiro Mitani, Daisuke Matsushita, Ryuji Ooba, Isao Kamioka, Yoshio Ozawa
  • Patent number: 8053827
    Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: November 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yuuichiro Mitani
  • Publication number: 20110241101
    Abstract: According to one embodiment, a semiconductor memory element includes a semiconductor layer, a tunnel insulator provided on the semiconductor layer, a charge accumulation film provided on the tunnel insulator having a film thickness of 0.9 nm or more and 2.8 nm or less and the charge accumulation film containing cubic HfO2 particles, a block insulator provided on the charge accumulation film, and a control electrode provided on the block insulator.
    Type: Application
    Filed: September 13, 2010
    Publication date: October 6, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsunehiro INO, Daisuke MATSUSHITA, Yasushi NAKASAKI, Masao SHINGU
  • Publication number: 20110240949
    Abstract: According to one embodiment, an information recording device includes first and second electrodes, a variable resistance layer between the first and second electrodes, and a control circuit which controls the variable resistance layer to n (n is a natural number except 1) kinds of resistance. The variable resistance layer comprises a material filled between the first and second electrodes, and particles arranged in a first direction from the first electrode to the second electrode in the material, and each of the particles has a resistance lower than that of the material. A resistance of the variable resistance layer is decided by a short between the first electrode and at least one of the particles.
    Type: Application
    Filed: March 18, 2011
    Publication date: October 6, 2011
    Inventors: Yuichiro MITANI, Daisuke Matsushita, Shosuke Fujii
  • Patent number: 7985650
    Abstract: A nonvolatile semiconductor memory device includes a floating gate electrode which is selectively formed on a main surface of a first conductivity type with a first gate insulating film interposed therebetween, a control gate electrode formed on the floating gate electrode with a second gate insulating film interposed therebetween, and source/drain regions of a second conductivity type which are formed in the main surface of the substrate in correspondence with the respective gate electrodes. The first gate electrode has a three-layer structure in which a silicon nitride film is held between silicon oxide films, and the silicon nitride film includes triple coordinate nitrogen bonds.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: July 26, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Daisuke Matsushita
  • Patent number: 7956405
    Abstract: A semiconductor storage element includes: a source region and a drain region provided in a semiconductor substrate; a tunnel insulating film provided on the semiconductor substrate between the source region and the drain region; a charge storage film provided on the tunnel insulating film; a block insulating film provided on the charge storage film; a gate electrode provided on the block insulating film; and a region containing a gas molecule, the region provided in a neighborhood of an interface between the charge storage film and the block insulating film.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: June 7, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunehiro Ino, Shosuke Fujii, Jun Fujiki, Akira Takashima, Masao Shingu, Daisuke Matsushita, Naoki Yasuda, Koichi Muraoka
  • Publication number: 20110089478
    Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.
    Type: Application
    Filed: December 20, 2010
    Publication date: April 21, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yuuichiro Mitani
  • Patent number: 7883967
    Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: February 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuuichiro Mitani, Daisuke Matsushita, Ryuji Ooba, Isao Kamioka, Yoshio Ozawa
  • Publication number: 20110003481
    Abstract: It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.
    Type: Application
    Filed: July 1, 2010
    Publication date: January 6, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Koichi Muraoka, Koichi Kato, Yasushi Nakasaki, Yuichiro Mitani