Abstract: Disclosed is a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other. The method comprises the steps of (S2) sorting the terminals according to the width thereof; and (S3˜S11) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal.

Abstract: Provided is a solubility-controallable compound being soluble in a solvent due to a solvent-philic group thereof, of which solubility in the solvent is irreversibly lowered when the group is removed by retro-Diels-Alder reaction.

Abstract: Disclosed is a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other. The method comprises the steps of (S2) sorting the terminals according to the width thereof; and (S3˜S11) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal.

Abstract: In a layout method for an LSI having a plurality of cells, automated arrangement of cells is performed on the basis of a netlist, which has cells and connection data therefor, and timing conditions, and, once a timing optimization processing is performed so that a plurality of cells are arranged on a chip, global wiring processing is implemented and the wiring congestion rate is analyzed. In addition, in small regions where a wiring congestion rate is so high that detailed wiring processing is judged to be difficult, cell rearrangement processing is implemented. Next, detailed wiring processing is performed with respect to the cells which have been rearranged. The rearrangement of cells is performed only in small regions with a high congestion rate, with the result that the overall cell arrangement in which timing is optimized is not changed markedly, whereby it is possible to reduce the probability of wiring being impossible in the course of the detailed wiring processing.

Abstract: Each binary carry logic circuit 20 of half adder circuits other than that for the least significant digit comprises a transfer gate 212 turned on when an input bit A2 is active and receiving a carry-in bit *C2 at its data input, and a transistor 23, turned on when the input bit A2 is inactive, connected between a power supply potential VDD and the data output of the transfer gate 212 a signal on which is a carry-out bit *C3. Transfer gates 212 to 214 of binary carry logic circuits other than that for the least significant digit are connected in chain, and are simultaneously on/off controlled by input bits A2 to A4, letting the carry-in bit *C2 from the least significant digit propagate through the transfer gate chain at a high speed.

Abstract: A method of designing a semiconductor integrated circuit includes the steps of generating a cell that includes a flip-flop and backup transistors, designing a circuit by use of the cell, and adjusting a timing by connecting the backup transistors to the flip-flop if there is a need to adjust timing of the flip-flop.

Abstract: A thin film formation apparatus includes a printing roll having an elastic letterpress of resin or rubber fitted at a part of a surface of a cylinder part and, an intaglio roll rotating while facing the printing roll, thereby transferring ink to a surface of the elastic letterpress through contact with the printing roll. The thin film formation apparatus further includes a pair of printing roll side contact bodies on a drum portion or a rotating shaft of the printing roll, and a pair of intaglio roll side contact bodies on a drum portion or a rotating shaft of the intaglio role. The printing roll side contact bodies and the intaglio roll side contact bodies continuously contact each other, at least before and during the contact of the elastic letterpress with the intaglio roll, to form a thin film of uniform film thickness.

Abstract: A partial random access memory includes a plurality of memory cells arrayed in matrix form, a plurality of pairs of bit lines extending in a column direction, each of the plurality of memory cells being coupled to corresponding one of pairs of bit lines, and a plurality of word lines including a plurality of first and second word lines. One first word line and one second word line are paired and arranged on both sides of an arrangement of the memory cells in a row direction. Each of the plurality of memory cells is connected to at least one of the first and second word lines. An activating circuit coupled to the plurality of word lines separately activates the first and second word lines, depending on an address signal supplied from an external circuit, thereby independently selecting the first and second word lines. An input/output circuit coupled to the plurality of bit lines writes input data into corresponding memory cells and reads out output data from corresponding memory cells.

Abstract: A master slice type semiconductor integrated circuit which includes a semiconductor chip, input/output cells arranged in a peripheral portion of the semiconductor chip, and basic cells arranged in an entire central portion of the semiconductor chip excluding the peripheral portion of the semiconductor chip. Each of the basic cells are formed by a complementary metal oxide semiconductor (MOS) forming part and an N-channel metal oxide semiconductor (NMOS) forming part. The CMOS forming part forms a CMOS by employing same number of P-channel metal oxide semiconductor (PMOS) transistors and NMOS transistors, while the NMOS forming part forms a plurality of NMOS transistors on at least one end of the CMOS forming part in a direction parallel to the CMOS forming part.