Patents by Inventor Daisuke Oshida

Daisuke Oshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120324241
    Abstract: A semiconductor device in related art has a problem that security on confidential information stored is insufficient. A semiconductor device of the present invention has a unique code which is unique to a device and generates unique code corresponding information from the unique code. The semiconductor device has a memory region in which specific information obtained by encrypting confidential information is stored in a region associated with the unique code corresponding information. The specific information read from the memory region is encrypted with the unique code corresponding information to generate the confidential information.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 20, 2012
    Inventors: Daisuke OSHIDA, Masayuki Hirokawa, Akira Yamazaki, Takashi Fujimori, Shigemasa Shiota, Shigeru Furuta
  • Patent number: 8329584
    Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: December 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
  • Publication number: 20120292765
    Abstract: Provided is a semiconductor device having a wiring layer formed of damascene wiring. The semiconductor device includes: a first wiring having a width equal to or larger than 0.5 ?m; a second wiring adjacent to the first wiring and arranged with a space less than 0.5 ?m from the first wiring; and a third wiring adjacent to the second wiring and arranged with a space equal to or smaller than 0.5 ?m from the first wiring. In the semiconductor device, the second wiring and the third wiring are structured to have the same electric potential.
    Type: Application
    Filed: July 30, 2012
    Publication date: November 22, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Daisuke OSHIDA
  • Patent number: 8299621
    Abstract: Provided is a semiconductor device having a wiring layer formed of damascene wiring. The semiconductor device includes: a first wiring having a width equal to or larger than 0.5 ?m; a second wiring adjacent to the first wiring and arranged with a space less than 0.5 ?m from the first wiring; and a third wiring adjacent to the second wiring and arranged with a space equal to or smaller than 0.5 ?m from the first wiring. In the semiconductor device, the second wiring and the third wiring are structured to have the same electric potential.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Daisuke Oshida
  • Publication number: 20120231623
    Abstract: A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.
    Type: Application
    Filed: May 24, 2012
    Publication date: September 13, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Daisuke OSHIDA, Toshiyuki TAKEWAKI, Shinji YOKOGAWA
  • Patent number: 8174011
    Abstract: In a positional offset measurement pattern unit formed in an insulating layer, a first interconnection is formed in the insulating layer. A via-plug is formed in the insulating layer so as to be electrically connected to the first interconnection. A second interconnection is formed in the insulating layer at substantially the same level as the first interconnection so as to be spaced from the first interconnection by a given distance. A voltage is applied between the first and second interconnections to measure a relative positional offset amount between the via-plug and the second interconnection.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: May 8, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Daisuke Oshida
  • Publication number: 20120015517
    Abstract: The semiconductor device includes an insulating film that is formed using a cyclic siloxane having a six-membered ring structure as a raw material; a trench that is formed in the insulating film; and a interconnect that is configured by a metal film embedded in the trench. In the semiconductor device, a modified layer is formed on a bottom surface of the trench, in which the number of carbon atoms and/or the number of nitrogen atoms per unit volume is larger than that inside the insulating film.
    Type: Application
    Filed: July 14, 2011
    Publication date: January 19, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Daisuke OSHIDA, Ippei KUME, Makoto UEKI, Manabu IGUCHI, Naoya INOUE, Takuya MARUYAMA, Toshiji TAIJI, Hirokazu KATSUYAMA
  • Publication number: 20110318900
    Abstract: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.
    Type: Application
    Filed: September 8, 2011
    Publication date: December 29, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Daisuke OSHIDA, Toshiyuki TAKEWAKI, Takuji ONUMA, Koichi OHTO
  • Patent number: 8030737
    Abstract: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: October 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Daisuke Oshida, Toshiyuki Takewaki, Takuji Onuma, Koichi Ohto
  • Publication number: 20110230051
    Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
    Type: Application
    Filed: June 2, 2011
    Publication date: September 22, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiyuki TAKEWAKI, Manabu IGUCHI, Daisuke OSHIDA, Hironori TOYOSHIMA, Masayuki HIROI, Takuji ONUMA, Hiroaki NANBA, Ichiro HONMA, Mieko HASEGAWA, Yasuaki TSUCHIYA, Toshiji TAIJI, Takaharu KUNUGI
  • Patent number: 7955980
    Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: June 7, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
  • Patent number: 7897475
    Abstract: A method of forming a semiconductor device, includes forming a lower electrode including a metal and a nitrogen on a semiconductor substrate, irradiating a reducing gas to a surface of the lower electrode, and irradiating a gas containing silicon to the surface of the lower electrode to form a projection containing silicide by reacting the metal with the silicon in an island shape on the surface of the lower electrode. Then, a capacitor film is formed on the lower electrode and the projection, and an upper electrode is formed on the capacitor film.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: March 1, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Daisuke Oshida, Toshiyuki Takewaki, Takuji Onuma, Koichi Ohto
  • Patent number: 7821101
    Abstract: A semiconductor device includes a lower electrode provided on a semiconductor substrate, an upper electrode provided on the lower electrode to overlap a part of the lower electrode, a first insulating film provided between the lower electrode and the upper electrode, and a second insulating film provided in contact with an upper part of the upper electrode and on the upper part of the lower electrode, and having a density higher than that of the first insulating film, the second insulating film covering a side surface and a top surface of the upper electrode.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Toshiyuki Takewaki, Daisuke Oshida, Takuji Onuma
  • Publication number: 20100117191
    Abstract: The present invention provides a semiconductor device that shows excellent manufacturing stability and has lower contact resistance, and a method for manufacturing the semiconductor device. The semiconductor device includes an upper interconnect, a lower interconnect, insulating layers interposed between the upper interconnect and the lower interconnect, a connecting portion that is formed in the insulating layers and connects the upper interconnect and the lower interconnect, and an element that is placed in one of the insulating layers and has a conductive layer connected to the connecting portion. The connecting portion is formed over the lower interconnect and the end portions of the conductive layer of the element, and is in contact with the upper face of the lower interconnect and the upper faces and side faces of the end portions of the conductive layer of the element.
    Type: Application
    Filed: November 12, 2009
    Publication date: May 13, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: DAISUKE OSHIDA, HIROYUKI KUNISHIMA, NORIO OKADA
  • Publication number: 20090305496
    Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
    Type: Application
    Filed: August 18, 2009
    Publication date: December 10, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Toshiyuki TAKEWAKI, Manabu IGUCHI, Daisuke OSHIDA, Hironori TOYOSHIMA, Masayuki HIROI, Takuji ONUMA, Hiroaki NANBA, Ichiro HONMA, Mieko HASEGAWA, Yasuaki TSUCHIYA, Toshiji TAIJI, Takaharu KUNUGI
  • Publication number: 20090294980
    Abstract: Provided is a semiconductor device having a wiring layer formed of damascene wiring. The semiconductor device includes: a first wiring having a width equal to or larger than 0.5 ?m; a second wiring adjacent to the first wiring and arranged with a space less than 0.5 ?m from the first wiring; and a third wiring adjacent to the second wiring and arranged with a space equal to or smaller than 0.5 ?m from the first wiring. In the semiconductor device, the second wiring and the third wiring are structured to have the same electric potential.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 3, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Daisuke OSHIDA
  • Patent number: 7601640
    Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
  • Publication number: 20090184421
    Abstract: A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.
    Type: Application
    Filed: January 8, 2009
    Publication date: July 23, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Daisuke Oshida, Toshiyuki Takewaki, Shinji Yokogawa
  • Publication number: 20080277762
    Abstract: A semiconductor device includes a lower electrode provided on a semiconductor substrate, an upper electrode provided on the lower electrode to overlap a part of the lower electrode, a first insulating film provided between the lower electrode and the upper electrode, and a second insulating film provided in contact with an upper part of the upper electrode and on the upper part of the lower electrode, and having a density higher than that of the first insulating film, the second insulating film covering a side surface and a top surface of the upper electrode.
    Type: Application
    Filed: April 11, 2008
    Publication date: November 13, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Toshiyuki Takewaki, Daisuke Oshida, Takuji Onuma
  • Publication number: 20080237793
    Abstract: A method of forming a semiconductor device, includes forming a lower electrode including a metal and a nitrogen on a semiconductor substrate, irradiating a reducing gas to a surface of the lower electrode, and irradiating a gas containing silicon to the surface of the lower electrode to form a projection containing silicide by reacting the metal with the silicon in an island shape on the surface of the lower electrode. Then, a capacitor film is formed on the lower electrode and the projection, and an upper electrode is formed on the capacitor film.
    Type: Application
    Filed: March 6, 2008
    Publication date: October 2, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Daisuke Oshida, Toshiyuki Takewaki, Takuji Onuma, Koichi Ohto