Patents by Inventor Daisuke Watanabe

Daisuke Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY
    Publication number: 20190080739
    Abstract: According to one embodiment, a magnetoresistive element includes: a first magnetic layer having a magnetization direction that is variable; a second magnetic layer having a magnetization direction that is invariable; a first non-magnetic layer provided between the first magnetic layer and the second magnetic layer; a third magnetic layer that fixes the magnetization direction of the second magnetic layer and that antiferromagnetically couples with the second magnetic layer; and a second non-magnetic layer provided between the second magnetic layer and the third magnetic layer. The second non-magnetic layer includes ruthenium (Ru) and a metal element.
    Type: Application
    Filed: March 9, 2018
    Publication date: March 14, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tadaaki OIKAWA, Young Min EEH, Kazuya SAWADA, Kenichi YOSHINO, Toshihiko NAGASE, Daisuke WATANABE
  • Lubrication structure and lubrication method for upper pin in piston crank mechanism of internal combustion engine
    Patent number: 10221734
    Abstract: A lubrication structure of the present invention is applied to a multi-link piston crank mechanism that has a upper link (3), a lower link (6) and a control link (7). Lubricating oil is supplied in an oil storing portion (21) formed between a pair of upper-pin pin boss portions (12) by a plate member (22) through an oil supply hole (19). By oscillating rotary motion of the upper link side pin boss portion (25) that is provided with an oil groove (29) on an end surface of the upper link side pin boss portion (25), the lubricating oil in the oil storing portion (21) is supplied to an upper pin (4).
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: March 5, 2019
    Assignee: NISSAN MOTOR CO., LTD.
    Inventors: Daisuke Watanabe, Shigeru Nakajima, Kazuto Waki, Yoshihiro Kobayashi
  • Techniques for establishing an external interface and a network interface within a connector
    Patent number: 10216675
    Abstract: A technique for establishing a network interface and an external interface in a connector is disclosed. A personal computer (PC) includes a device controller for controlling data transmission with a peripheral device and a network device, and a receptacle including multiple pins for connecting data channels of the device controller to the peripheral device through the external interface and the network device through the network interface. The PC further includes a crossbar switch for switching the data channels to establish the external interface and the network interface in the receptacle. The external interface complies with the USB standards, and the network interface complies with the Ethernet standards.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: February 26, 2019
    Assignee: LENOVO (SINGAPORE) PTE LTD
    Inventors: Yasumichi Tsukamoto, Luis Antonio Hernandez, Tomoki Harada, Daisuke Watanabe
  • Electronic device
    Patent number: 10203380
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 12, 2019
    Assignees: SK Hynix Inc., Toshiba Memory Corporation
    Inventors: Ku-Youl Jung, Guk-Cheon Kim, Toshihiko Nagase, Daisuke Watanabe, Won-Joon Choi, Youngmin Eeh, Kazuya Sawada
  • Magnetic storage device and manufacturing method of magnetic storage device
    Patent number: 10199568
    Abstract: According to one embodiment, a magnetic storage device includes a substrate, a dummy contact disposed on a top surface of the substrate, extending linearly in a direction substantially perpendicular to the top surface of the substrate, and floating electrically, and a magnetoresistive effect element included in a layer and insulated from the dummy contact, wherein the layer is disposed on the top surface of the dummy contact.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: February 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Nagamine, Young Min Eeh, Daisuke Watanabe, Kazuya Sawada, Toshihiko Nagase
  • BATTERY PACKAGING MATERIAL, BATTERY, AND METHOD FOR PRODUCING BATTERY PACKAGING MATERIAL
    Publication number: 20190036086
    Abstract: A battery packaging material that is excellent in electrolytic solution resistance and ink printing characteristics of the surface. A battery packaging material comprising a laminate having at least a protective layer, a base material layer, a barrier layer, and a heat-sealable resin layer in this order, wherein a maximum value A of absorbance detected in an infrared wavenumber range of 2800 to 3000 cm?1 and a maximum value B of absorbance detected in an infrared wavenumber range of 2200 to 2300 cm?1 satisfy the relation: 0.05?B/A?0.75, as measured from an outermost surface of the protective layer, using attenuated total reflection Fourier transform infrared spectroscopy.
    Type: Application
    Filed: February 17, 2017
    Publication date: January 31, 2019
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventors: Shunsuke UEDA, Rikiya YAMASHITA, Daisuke WATANABE
  • AMPLIFIER
    Publication number: 20190028070
    Abstract: An amplifier according to an embodiment of the present disclosure includes a first transistor and a first matching circuit. The first matching circuit is connected between an input terminal and a control terminal of the first transistor. A first terminal of the first transistor is connected to a ground. A second terminal of the first transistor is connected to a power supply and an output terminal. The first matching circuit includes a first inductor, a second inductor, and a first switch. The first inductor has an end connected to the control terminal. The second inductor has an end connected to the other end of the first inductor. The first switch is configured to selectively switch between electrical continuity between the input terminal and the other end of the first inductor and electrical continuity between the input terminal and the other end of the second inductor.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 24, 2019
    Inventors: Daisuke WATANABE, Ken WAKAKI
  • SEMICONDUCTOR DEVICE HAVING RARE EARTH OXIDE LAYER AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20190019841
    Abstract: A semiconductor device includes a first rare earth oxide layer, a first magnetic layer adjacent to the first rare earth oxide layer, a second rare earth oxide layer, a second magnetic layer adjacent to the second rare earth oxide layer, and a nonmagnetic layer. The first magnetic layer is disposed between the first rare earth oxide layer and the nonmagnetic layer and is oriented in a crystal surface which is the same as a crystal surface of the nonmagnetic layer. The second magnetic layer is disposed between the second rare earth oxide layer and the nonmagnetic layer and is oriented in a crystal surface which is the same as a crystal surface of the nonmagnetic layer. The nonmagnetic layer is disposed between the first magnetic layer and the second magnetic layer.
    Type: Application
    Filed: September 9, 2018
    Publication date: January 17, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Youngmin EEH, Toshihiko NAGASE, Daisuke WATANABE, Kazuya SAWADA, Kenichi YOSHINO, Tadaaki OIKAWA, Hiroyuki OHTORI
  • Switch module
    Patent number: 10181839
    Abstract: A switch module includes a first terminal, first and second filters, and first and second switches. Impedance of the first filter for a signal in a stop band is capacitive. When the first switch is turned OFF, impedance of the first switch is capacitive, and impedance of the first filter seen from an end portion of the first switch connected to the first filter is not in a short state and impedance of the first filter seen from the first terminal is in an open state.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 15, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Tomita, Daisuke Watanabe
  • Magnetoresistive element and memory device
    Patent number: 10170519
    Abstract: According to one embodiment, a magnetoresistive element includes a first metal layer having a body-centered cubic structure, a second metal layer having a hexagonal close-packed structure on the first metal layer, a metal nitride layer on the second metal layer, a first magnetic layer on the metal nitride layer, an insulating layer on the first magnetic layer, and a second magnetic layer on the insulating layer.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: January 1, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Youngmin Eeh, Toshihiko Nagase, Daisuke Watanabe, Koji Ueda, Makoto Nagamine, Kazuya Sawada
  • Electronic device and method for fabricating the same
    Patent number: 10170691
    Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: January 1, 2019
    Assignees: SK Hynix Inc., TOSHIBA MEMORY CORPORATION
    Inventors: Jong-Koo Lim, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Toshihiko Nagase, Youngmin Eeh, Daisuke Watanabe, Kazuya Sawada, Makoto Nagamine
  • Amplifier
    Patent number: 10110176
    Abstract: An amplifier according to an embodiment of the present disclosure includes a first transistor and a first matching circuit. The first matching circuit is connected between an input terminal and a control terminal of the first transistor. The first matching circuit includes a first inductor, a second inductor, and a first switch. The first inductor has an end connected to the control terminal. The second inductor has an end connected to the other end of the first inductor. The first switch is configured to selectively switch between electrical continuity between the input terminal and the other end of the first inductor and electrical continuity between the input terminal and the other end of the second inductor.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: October 23, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Daisuke Watanabe, Ken Wakaki
  • Magnetoresistive element
    Patent number: 10103318
    Abstract: According to one embodiment, there is provided a magnetoresistive element, including a first magnetic layer, a nonmagnetic layer on the first magnetic layer, and a second magnetic layer on the nonmagnetic layer, wherein one of the first and second magnetic layers include one of Co and Fe, and a material having a higher standard electrode potential than Co and Fe.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 16, 2018
    Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX, INC.
    Inventors: Daisuke Watanabe, Yang Kon Kim, Makoto Nagamine, Youngmin Eeh, Koji Ueda, Toshihiko Nagase, Kazuya Sawada, Guk Cheon Kim, Bo Mi Lee, Won Joon Choi
  • INFORMATION PROCESSING APPARATUS, MEASURING APPARATUS, SYSTEM, INTERFERENCE DETERMINATION METHOD, AND ARTICLE MANUFACTURING METHOD
    Publication number: 20180290307
    Abstract: Accuracy in interference determination between a hand gripping a workpiece and nearby objects is increased. An information processing apparatus includes a measuring unit configured to decide an object to be gripped among a plurality of objects on the basis of a first image of the imaged objects, a specifying unit configured to specify an attention area for determining, when a gripping device grips the object to be gripped, whether the gripping device interferes with objects near the object to be gripped, a controller configured to change an imaging range of an imaging device on the basis of the attention area, and a determination unit configured to determine, when the gripping device grips the object to be gripped, whether the gripping device interferes with the objects near the object to be gripped on the basis of a second image of an object imaged in a changed imaging range.
    Type: Application
    Filed: April 5, 2018
    Publication date: October 11, 2018
    Inventor: Daisuke Watanabe
  • ELECTRONIC DEVICE
    Publication number: 20180284199
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.
    Type: Application
    Filed: December 14, 2017
    Publication date: October 4, 2018
    Inventors: Ku-Youl JUNG, Guk-Cheon KIM, Toshihiko NAGASE, Daisuke WATANABE, Won-Joon CHOI, Youngmin EEH, Kazuya SAWADA
  • Magnetoresistive element
    Patent number: 10090459
    Abstract: A magnetoresistive element includes a storage layer as a ferromagnetic layer which has magnetic anisotropy perpendicular to film planes, and in which a magnetization direction is variable, a reference layer as a ferromagnetic layer which has magnetic anisotropy perpendicular to film planes, and in which a magnetization direction is invariable, a tunnel barrier layer as a nonmagnetic layer formed between the storage layer and the reference layer, and a first underlayer formed on a side of the storage layer, which is opposite to a side facing the tunnel barrier layer, and containing amorphous W.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Watanabe, Youngmin Eeh, Kazuya Sawada, Koji Ueda, Toshihiko Nagase
  • MAGNETIC MEMORY DEVICE
    Publication number: 20180277745
    Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistive element, the magnetoresistive element including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. The first magnetic layer includes first and second sub-magnetic layers each containing at least iron (Fe) and boron (B), and a concentration of boron (B) contained in the first sub-magnetic layer is different from a concentration of boron (B) contained in the second sub-magnetic layer.
    Type: Application
    Filed: September 12, 2017
    Publication date: September 27, 2018
    Applicants: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.
    Inventors: Tadaaki OIKAWA, Toshihiko NAGASE, Youngmin EEH, Daisuke WATANABE, Kazuya SAWADA, Kenichi YOSHINO, Hiroyuki OHTORI, Yang Kon KIM, Ku Youl JUNG, Jong Koo LIM, Jae Hyoung LEE, Soo Man SEO, Sung Woong CHUNG, Tae Young LEE
  • BOLT FASTENING METHOD FOR LOWER LINK
    Publication number: 20180252156
    Abstract: A jig (31) is placed on a cylinder block (11) set in an inverted position, and a crankshaft (5) is lifted upward from a main bearing part (17) and held at a predetermined height position. A lower link (7) temporarily fitted to a crank pin (6) in the previous step is rotated about the crank pin (6) as a cener by a robot hand, and held in a predetermined inclined position in which a dividing surface (28) becomes vertical. In this state, a pair of bolts (29) is horizontally fastened from the right and the left by using a nut runner (55).
    Type: Application
    Filed: September 16, 2015
    Publication date: September 6, 2018
    Applicant: NISSAN MOTOR CO., LTD.
    Inventors: Mitsuo TOUSE, Yoshihiro KOBAYASHI, Shigeru NAKAJIMA, Kazuhiko TAKASHIMA, Kazuto WAKI, Daisuke WATANABE, Takeshi CHIHARA, Kousuke INOUE
  • TETRACARBOXYLIC DIANHYDRIDE, CARBONYL COMPOUND, POLYAMIC ACID, POLYIMIDE, METHODS FOR PRODUCING THE SAME, SOLUTION USING POLYAMIC ACID, AND FILM USING POLYIMIDE
    Publication number: 20180237638
    Abstract: A tetracarboxylic dianhydride, which is a compound represented by the following general formula (1): [in the formula (1), multiple R1s each independently represent hydrogen atom or the like, and R2 and R3 each independently represent a hydrogen atom or the like].
    Type: Application
    Filed: August 5, 2016
    Publication date: August 23, 2018
    Applicant: JXTG NIPPON OIL & ENERGY CORPORATION
    Inventors: Yusuke MATSUO, Masaki NOGUCHI, Daisuke WATANABE, Ryuichi UENO, Shinichi KOMATSU
  • HOLOGRAPHIC OPTICAL ELEMENT AND METHOD FOR PRODUCING THE SAME
    Publication number: 20180217312
    Abstract: The present invention relates to a holographic optical element having a volume hologram recording layer containing a photopolymer, and at least one adjacent layer that is in contact with the volume hologram recording layer and contains a resin and a thiol compound. According to the present invention, a means for improving the diffraction efficiency of a holographic optical element having a volume hologram recording layer is provided.
    Type: Application
    Filed: July 12, 2016
    Publication date: August 2, 2018
    Inventors: Saburou HIRAOKA, Kenichi ONAKA, Daisuke WATANABE, Yuya KUBO, Kishio TAMURA