Patents by Inventor Damion T. Searls
Damion T. Searls has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9478488Abstract: In one embodiment, the present invention includes a semiconductor device mounted to a first side of a circuit board; and at least one voltage regulator device mounted to a second side of the circuit board, the second side opposite to the first side. Examples of the voltage regulator devices include output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.Type: GrantFiled: January 14, 2014Date of Patent: October 25, 2016Assignee: Intel CorporationInventors: Damion T. Searls, Edward P. Osburn
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Publication number: 20140124942Abstract: In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.Type: ApplicationFiled: January 14, 2014Publication date: May 8, 2014Inventors: Damion T. Searls, Edward P. Osburn
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Patent number: 7886809Abstract: In one embodiment, an apparatus includes a phase change material, a plurality of particles intermixed with the phase change material, and a conductive structure encapsulating the phase change material. The conductive structure includes a cavity including a cone shape. In one embodiment, a method includes forming a conductive structure having a cavity, injecting a phase change material into the cavity, injecting a plurality of spheres into the cavity, and sealing the cavity.Type: GrantFiled: October 31, 2007Date of Patent: February 15, 2011Assignee: Intel CorporationInventors: Damion T. Searls, Terrance J. Dishongh, David Pullen
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Patent number: 7791585Abstract: A method of fabricating a flexible display, the method comprising selecting a first flexible sheet and a second flexible sheet; and forming a number of magnetic display elements having magnetically controllable reflectivity between the first flexible sheet and the second flexible sheet. In some embodiments, a display includes pixels having a magnetically controllable reflectivity. The pixels are formed between a pair of flexible non-conductive sheets. Each of the magnetically controllable pixels includes a flexible ring located between the flexible non-conductive sheets. Each of the magnetically controllable pixels also includes magnetic particles located within the flexible ring. The location of the magnetic particles with respect to the flexible non-conductive sheets determines the reflectivity of the pixel. The display is especially suitable for use in connection with portable electronic devices.Type: GrantFiled: November 17, 2006Date of Patent: September 7, 2010Assignee: Intel CorporationInventors: James D. Jackson, Terrance J. Dishongh, Damion T. Searls
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Patent number: 7638884Abstract: A thin semiconductor device package, comprising a thin substrate at least one thin die coupled with the substrate and having a perimeter dimension less than that of the substrate a mold material provided at a surface of the substrate adjacent to the perimeter of the die so that a surface of the mold material is coplanar with a surface of the die, and at least one electrically conductive pathway having at least one first terminal end configured to provide electrical continuity with the conductive element and at least one second terminal end formed at a surface of the mold material, the pathway extending from the first terminal end to the second terminal end.Type: GrantFiled: January 5, 2009Date of Patent: December 29, 2009Assignee: Intel CorporationInventors: James D. Jackson, Damion T. Searls, Yoshihiro Tomita
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Patent number: 7538440Abstract: A printed circuit board having at least one conductive region covered in solder paste has preformed solder elements placed on the solder paste in the conductive region. A component package is placed onto the printed circuit board over the conductive region and the solder is reflowed, forming a wide solder interconnection between the component and the conductive region of the printed circuit board.Type: GrantFiled: April 30, 2003Date of Patent: May 26, 2009Assignee: Intel CorporationInventors: Dudi I. Amir, Damion T. Searls
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Publication number: 20090109643Abstract: A thin semiconductor device package, comprising a thin substrate at least one thin die coupled with the substrate and having a perimeter dimension less than that of the substrate a mold material provided at a surface of the substrate adjacent to the perimeter of the die so that a surface of the mold material is coplanar with a surface of the die, and at least one electrically conductive pathway having at least one first terminal end configured to provide electrical continuity with the conductive element and at least one second terminal end formed at a surface of the mold material, the pathway extending from the first terminal end to the second terminal end.Type: ApplicationFiled: January 5, 2009Publication date: April 30, 2009Inventors: James D. Jackson, Damion T. Searls, Yoshihiro Tomita
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Patent number: 7517732Abstract: A thin semiconductor device package, comprising a thin substrate, at least one thin die coupled with the substrate and having a perimeter dimension less than that of the substrate, a mold material provided at a surface of the substrate adjacent to the perimeter of the die so that a surface of the mold material is coplanar with a surface of the die, and at least one electrically conductive pathway having at least one first terminal end configured to provide electrical continuity with the conductive element and at least one second terminal end formed at a surface of the mold material, the pathway extending from the first terminal end to the second terminal end.Type: GrantFiled: April 12, 2006Date of Patent: April 14, 2009Assignee: Intel CorporationInventors: James D. Jackson, Damion T. Searls, Yoshihiro Tomita
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Patent number: 7495318Abstract: The invention relates to an apparatus and method for improving AC coupling between adjacent signal traces and between plane splits and signals spanning plane splits on circuit boards. A circuit board includes adjacent conductive means and an oxide means interposed there between. The oxide means is a copper oxide, e.g., cupric or cuprous oxide. In one embodiment, the adjacent conductive means are adjacent voltage reference planes with a split interposed between the conductive means. The copper oxide fills the split. In another embodiment, the adjacent conductive means are differential signal traces. The copper oxide fills a gap between the differential signal traces. The copper oxide is a non-conductive material with an increased dielectric constant as compared to other common dielectric materials used as fillers. The increased dielectric constant increases capacitance, in turn, increasing AC coupling.Type: GrantFiled: May 2, 2005Date of Patent: February 24, 2009Assignee: Intel CorporationInventors: Weston Roth, Damion T. Searls, James D. Jackson
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Patent number: 7316265Abstract: In one embodiment, a method includes forming a conductive structure having a cavity, injecting a phase change material into the cavity, injecting a plurality of spheres into the cavity, and sealing the cavity.Type: GrantFiled: November 17, 2003Date of Patent: January 8, 2008Assignee: Intel CorporationInventors: Damion T. Searls, Terrance J. Dishongh, David Pullen
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Patent number: 7255492Abstract: A method includes providing a light pipe having a metallized end surface, and soldering the metallized end surface of the light pipe to a surface of a substrate. Other embodiments are described and claimed.Type: GrantFiled: August 2, 2004Date of Patent: August 14, 2007Assignee: Intel CorporationInventors: Weston C. Roth, Damion T. Searls, Thomas O. Morgan, James D. Jackson
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Patent number: 7158111Abstract: A display includes pixels having a magnetically controllable reflectivity. The pixels are formed between a pair of flexible non-conductive sheets. Each of the magnetically controllable pixels includes a flexible ring located between the flexible non-conductive sheets. Each of the magnetically controllable pixels also includes magnetic particles located within the flexible ring. The location of the magnetic particles with respect to the flexible non-conductive sheets determines the reflectivity of the pixel. The display is especially suitable for use in connection with portable electronic devices.Type: GrantFiled: March 30, 2000Date of Patent: January 2, 2007Assignee: Intel CorporationInventors: James D. Jackson, Terrance J. Dishongh, Damion T. Searls
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Patent number: 7135758Abstract: A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.Type: GrantFiled: February 9, 2004Date of Patent: November 14, 2006Assignee: Intel CorporationInventors: Damion T. Searls, Weston C. Roth, James Daniel Jackson
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Patent number: 7122891Abstract: Apparatus and methods of fabricating antennae embedded within a ceramic material, such as a low temperature co-fired ceramic. Such ceramic material has a low coefficient of thermal expansion which reduces expansion and contraction stresses that can cause the signal transmission frequency to change and thereby affecting proper signal transmission.Type: GrantFiled: December 23, 2003Date of Patent: October 17, 2006Assignee: Intel CorporationInventors: Terrance Dishongh, Weston C. Roth, Damion T. Searls, Tom E. Pearson
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Patent number: 6996899Abstract: Solder bumps are created on a substrate of an electronic assembly having lengths that are longer than the widths. The solder bumps are created by locating solder balls of power or ground connections close to one another so that, upon reflow, the solder balls combine. Signal solder balls however remain separated. Capacitors are created by locating power solder bumps adjacent ground solder bumps and extending parallel to one another.Type: GrantFiled: March 25, 2003Date of Patent: February 14, 2006Assignee: Intel CorporationInventors: Damion T. Searls, Terrance J. Dishongh, James D. Jackson
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Patent number: 6913999Abstract: A semiconductor substrate with integrated circuit devices on its front side and a high thermal conductivity layer such as diamond on its back side, with components such as capacitors embedded in the high thermal conductivity layer and coupled to the front side integrated circuits with vias through the substrate.Type: GrantFiled: September 24, 2003Date of Patent: July 5, 2005Assignee: Intel CorporationInventors: Damion T. Searls, Prateek J. Dujari, Bin Lian
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Patent number: 6905979Abstract: The invention relates to an apparatus and method for improving AC coupling between adjacent signal traces and between plane splits and signals spanning plane splits on circuit boards. A circuit board includes adjacent conductive means and an oxide means interposed there between. The oxide means is a copper oxide, e.g., cupric or cuprous oxide. In one embodiment, the adjacent conductive means are adjacent voltage reference planes with a split interposed between the conductive means. The copper oxide fills the split. In another embodiment, the adjacent conductive means are differential signal traces. The copper oxide fills a gap between the differential signal traces. The copper oxide is a non-conductive material with an increased dielectric constant as compared to other common dielectric materials used as fillers. The increased dielectric constant increases capacitance, in turn, increasing AC coupling.Type: GrantFiled: December 23, 2002Date of Patent: June 14, 2005Assignee: Intel CorporationInventors: Weston Roth, Damion T. Searls, James D. Jackson
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Patent number: 6856016Abstract: An embodiment of the present invention described and shown in the specification and drawings is a process and a package for facilitating cooling and grounding of a semiconductor die using carbon nanotubes in a thermal interface layer between the die and a thermal management aid. The embodiments that are disclosed have the carbon nanotubes positioned and sized to utilize their high thermal and electrical conductance to facilitate the flow of heat and current to the thermal management aid. One embodiment disclosed has the carbon nanotubes mixed with a paste matrix before being applied. Another disclosed embodiment has the carbon nanotubes grown on the surface of the semiconductor die.Type: GrantFiled: July 2, 2002Date of Patent: February 15, 2005Inventors: Damion T. Searls, Terrance J. Dishongh, James Daniel Jackson
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Publication number: 20040216917Abstract: A printed circuit board having at least one conductive region covered in solder paste has preformed solder elements placed on the solder paste in the conductive region. A component package is placed onto the printed circuit board over the conductive region and the solder is reflowed, forming a wide solder interconnection between the component and the conductive region of the printed circuit board.Type: ApplicationFiled: April 30, 2003Publication date: November 4, 2004Inventors: Dudi I. Amir, Damion T. Searls
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Patent number: 6793505Abstract: A socket may comprise an array of first contacts and a set of second contacts having a greater conductive cross-sectional area than the first contacts. The set of second contacts may also have a greater conductive area efficiency than the array of first contacts, with conductive area efficiency defined as a total conductive cross-sectional area divided by a total occupied area. The array of first contacts may electrically couple signal pads of a land grid array (LGA) component with a plurality of signal lines in a printed circuit board (PCB). The set of second contacts may electrically couple power delivery land pads of the LGA component with power and ground planes of the PCB.Type: GrantFiled: March 26, 2002Date of Patent: September 21, 2004Assignee: Intel CorporationInventors: Terrance J. Dishongh, Weston C. Roth, Damion T. Searls