Patents by Inventor Damion T. Searls

Damion T. Searls has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6793503
    Abstract: A socket may comprise an array of first contacts and a set of second contacts having a greater conductive cross-sectional area than the first contacts. The set of second contacts may also have a greater conductive area efficiency than the array of first contacts, with conductive area efficiency defined as a total conductive cross-sectional area divided by a total occupied area. The array of first contacts may electrically couple signal pads of a land grid array (LGA) component with a plurality of signal lines in a printed circuit board (PCB). The set of second contacts may electrically couple power delivery land pads of the LGA component with power and ground planes of the PCB.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: September 21, 2004
    Assignee: Intel Corporation
    Inventors: Terrance J. Dishongh, Weston C. Roth, Damion T. Searls
  • Publication number: 20040155335
    Abstract: A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.
    Type: Application
    Filed: February 9, 2004
    Publication date: August 12, 2004
    Applicant: Intel Corporation
    Inventors: Damion T. Searls, Weston C. Roth, James Daniel Jackson
  • Patent number: 6774310
    Abstract: An enhanced joint thickness lead used for surface mounting electronic devices to a substrate, wherein a portion of the enhanced joint thickness lead that is substantially parallel to the substance. The enhanced joint thickness lead includes an arcuate structure, which provides an enhanced joint thickness for the solder used to connect the lead to the substrate. The enhanced joint thickness of the solder results in a more robust attachment of the electronic device.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: August 10, 2004
    Assignee: Intel Corporation
    Inventors: Terrance J. Dishongh, Prateek J. Dujari, Bin Lian, Damion T. Searls
  • Publication number: 20040119147
    Abstract: The invention relates to an apparatus and method for improving AC coupling between adjacent signal traces and between plane splits and signals spanning plane splits on circuit boards. A circuit board includes adjacent conductive means and an oxide means interposed there between. The oxide means is a copper oxide, e.g., cupric or cuprous oxide. In one embodiment, the adjacent conductive means are adjacent voltage reference planes with a split interposed between the conductive means. The copper oxide fills the split. In another embodiment, the adjacent conductive means are differential signal traces. The copper oxide fills a gap between the differential signal traces. The copper oxide is a non-conductive material with an increased dielectric constant as compared to other common dielectric materials used as fillers. The increased dielectric constant increases capacitance, in turn, increasing AC coupling.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Applicant: Intel Corporation
    Inventors: Weston Roth, Damion T. Searls, James D. Jackson
  • Patent number: 6752635
    Abstract: A conventional land grid array (LGA) socket assembly uses the same socket contact in the power delivery area and the signal delivery area. Using low current socket contacts in the power delivery area may create self-heating and limit power delivery from a printed circuit board (PCB) to an IC package mounted in the socket. Embodiments of the present invention are directed to an LGA socket assembly that has a separate power delivery contact, which includes contact pins and contacts pads that are ganged using a cross beam to form a comb-shaped contact. In an alternative embodiment of the present invention, an LGA socket assembly has a shorter channel in the power delivery area than in known LGA socket assemblies. In still another embodiment, an LGA socket assembly has a shorter channel in the power delivery area in the signal delivery area.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: June 22, 2004
    Assignee: Intel Corporation
    Inventors: Damion T. Searls, Thomas G. Ruttan, Jiteender P. Manik
  • Patent number: 6730860
    Abstract: Solder bumps are created on a substrate of an electronic assembly having lengths that are longer than the widths. The solder bumps are created by locating solder balls of power or ground connections close to one another so that, upon reflow, the solder balls combine. Signal solder balls however remain separated. Capacitors are created by locating power solder bumps adjacent ground solder bumps and extending parallel to one another.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: May 4, 2004
    Assignee: Intel Corporation
    Inventors: Damion T. Searls, Terrance J. Dishongh, James D. Jackson
  • Patent number: 6731221
    Abstract: An electrically modifiable label. In some embodiments, an electrically modifiable label may be applied to or form a part of products that have configurable or otherwise dynamic characteristics. That is, characteristics or desirability that vary over time or characteristics that may be selected or determined at or after advanced stages of manufacturing processes.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: May 4, 2004
    Assignee: Intel Corporation
    Inventors: Terrance J. Dioshongh, Damion T. Searls, Bin Lian
  • Patent number: 6713871
    Abstract: A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: March 30, 2004
    Assignee: Intel Corporation
    Inventors: Damion T. Searls, Weston C. Roth, James Daniel Jackson
  • Publication number: 20040056272
    Abstract: A semiconductor substrate with integrated circuit devices on its front side and a high thermal conductivity layer such as diamond on its back side, with components such as capacitors embedded in the high thermal conductivity layer and coupled to the front side integrated circuits with vias through the substrate.
    Type: Application
    Filed: September 24, 2003
    Publication date: March 25, 2004
    Inventors: Damion T. Searls, Prateek J. Dujari, Bin Lian
  • Publication number: 20040017295
    Abstract: An electrically modifiable label. In some embodiments, an electrically modifiable label may be applied to or form a part of products that have configurable or otherwise dynamic characteristics. That is, characteristics or desirability that vary over time or characteristics that may be selected or determined at or after advanced stages of manufacturing processes.
    Type: Application
    Filed: July 16, 2003
    Publication date: January 29, 2004
    Inventors: Terrance J. Dishongh, Damion T. Searls, Bin Lian
  • Publication number: 20040005736
    Abstract: An embodiment of the present invention described and shown in the specification and drawings is a process and a package for facilitating cooling and grounding of a semiconductor die using carbon nanotubes in a thermal interface layer between the die and a thermal management aid. The embodiments that are disclosed have the carbon nanotubes positioned and sized to utilize their high thermal and electrical conductance to facilitate the flow of heat and current to the thermal management aid. One embodiment disclosed has the carbon nanotubes mixed with a paste matrix before being applied. Another disclosed embodiment has the carbon nanotubes grown on the surface of the semiconductor die.
    Type: Application
    Filed: July 2, 2002
    Publication date: January 8, 2004
    Applicant: Intel Corporation
    Inventors: Damion T. Searls, Terrance J. Dishongh, James Daniel Jackson
  • Patent number: 6672370
    Abstract: A heat sink includes a heat sink body including a number of fins and a cavity for holding a phase change material and a number of particles to enhance the mixing of the phase change material during the operation of the heat sink. In operation, the body of the heat sink conducts thermal energy to the phase change material. The energy is absorbed during the phase change of the phase change material. After absorbing energy and changing to a liquid state, the phase change material continues to dissipate energy by convection. The convection currents in the cavity are directed by the shape of the cavity surfaces and enhanced by the particles intermixed with the phase change material.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: January 6, 2004
    Assignee: Intel Corporation
    Inventors: Damion T. Searls, Terrance J. Dishongh, David Pullen
  • Publication number: 20030218235
    Abstract: A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.
    Type: Application
    Filed: May 21, 2002
    Publication date: November 27, 2003
    Applicant: Intel Corporation
    Inventors: Damion T. Searls, Weston C. Roth, James Daniel Jackson
  • Patent number: 6649937
    Abstract: A semiconductor substrate with integrated circuit devices on its front side and a high thermal conductivity layer such as diamond on its back side, with components such as capacitors embedded in the high thermal conductivity layer and coupled to the front side integrated circuits with vias through the substrate.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: November 18, 2003
    Assignee: Intel Corporation
    Inventors: Damion T. Searls, Prateek J. Dujari, Bin Lian
  • Publication number: 20030207598
    Abstract: A socket may comprise an array of first contacts and a set of second contacts having a greater conductive cross-sectional area than the first contacts. The set of second contacts may also have a greater conductive area efficiency than the array of first contacts, with conductive area efficiency defined as a total conductive cross-sectional area divided by a total occupied area. The array of first contacts may electrically couple signal pads of a land grid array (LGA) component with a plurality of signal lines in a printed circuit board (PCB). The set of second contacts may electrically couple power delivery land pads of the LGA component with power and ground planes of the PCB.
    Type: Application
    Filed: May 27, 2003
    Publication date: November 6, 2003
    Inventors: Terrance J. Dishongh, Weston C. Roth, Damion T. Searls
  • Publication number: 20030186568
    Abstract: A socket may comprise an array of first contacts and a set of second contacts having a greater conductive cross-sectional area than the first contacts. The set of second contacts may also have a greater conductive area efficiency than the array of first contacts, with conductive area efficiency defined as a total conductive cross-sectional area divided by a total occupied area. The array of first contacts may electrically couple signal pads of a land grid array (LGA) component with a plurality of signal lines in a printed circuit board (PCB). The set of second contacts may electrically couple power delivery land pads of the LGA component with power and ground planes of the PCB.
    Type: Application
    Filed: March 26, 2002
    Publication date: October 2, 2003
    Inventors: Terrance J. Dishongh, Weston C. Roth, Damion T. Searls
  • Publication number: 20030183823
    Abstract: A semiconductor substrate with integrated circuit devices on its front side and a high thermal conductivity layer such as diamond on its back side, with components such as capacitors embedded in the high thermal conductivity layer and coupled to the front side integrated circuits with vias through the substrate.
    Type: Application
    Filed: March 26, 2002
    Publication date: October 2, 2003
    Inventors: Damion T. Searls, Prateek J. Dujari, Bin Lian
  • Patent number: 6627822
    Abstract: A electronic assembly is disclosed and claimed. The electronic assembly includes a first substrate and a second substrate. A plurality of power connections are coupled between the first substrate and the second substrate and a multiplicity of signal connections separate from the plurality of power connections are also coupled between the first substrate and the second substrate. Each of the plurality of power connections have a substantially different size and shape compared to each of the multiplicity of signal connections.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: September 30, 2003
    Assignee: Intel Corporation
    Inventors: James Daniel Jackson, Terrance J. Dishongh, Damion T. Searls
  • Patent number: 6624643
    Abstract: Photon emissions from a backside of a silicon device or integrated circuit are detected. The photon emissions can be used for a technique to read output information from the silicon device, as the photon emissions from part of an output signal path for the silicon device. The emitted photons pass through openings of a mask positioned over the backside of the silicon device, and are detected by a photodetector array. Electrical signals are generated from the detected photons, and can be converted to optical signals for subsequent transmission from optical transmitters coupled to the photodetector.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: September 23, 2003
    Assignee: Intel Corporation
    Inventors: Terrence J. Dishongh, Prateek Dujari, Bin C. Lian, Damion T. Searls
  • Patent number: 6614657
    Abstract: The heat sink is described which is used to cool an electronic component of a computer. The heat sink is constructed from a metal sheet which is bent so as to have a horizontal thermally conductive plate and four walls extending upwardly from the plate and jointly define an enclosure. Openings are formed in the walls through which air can flow by natural convection.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: September 2, 2003
    Assignee: Intel Corporation
    Inventors: Damion T. Searls, Terrance J. Dishongh, James D. Jackson