Abstract: A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.

Abstract: A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include a stack of layers having a phase change layer or phase change region that includes nitrogen. The presence of the nitrogen increases crystallization rates of the phase change material during transition from an amorphous state to crystalline state, thus increasing the overall speed of the memory device. In some embodiments, the phase change layer includes a small amount of nitrogen homogenously dispersed within the layer. In some other embodiments, the phase change layer includes one or more regions having nitrogen introduced during the deposition process. In some other embodiments, separate material layers that include nitrogen are provided on one or more sides of the phase change layer.

Abstract: A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.

Abstract: A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.

Abstract: Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing materials onto microfeature workpieces are disclosed herein. In one embodiment, a method includes depositing molecules of a gas onto a microfeature workpiece in the reaction chamber and selectively irradiating a first portion of the molecules on the microfeature workpiece in the reaction chamber with a selected radiation without irradiating a second portion of the molecules on the workpiece with the selected radiation. The first portion of the molecules can be irradiated to activate the portion of the molecules or desorb the portion of the molecules from the workpiece. The first portion of the molecules can be selectively irradiated by impinging the first portion of the molecules with a laser beam or other energy source.

Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.

Abstract: Methods for forming ruthenium films and semiconductor devices, such as capacitors, that include the films are provided.

Abstract: Methods for forming ruthenium films and semiconductor devices such as capacitors that include the films are provided.

Abstract: Methods for forming ruthenium films and semiconductor devices such as capacitors that include the films are provided.

Abstract: Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a dielectric constant higher than a dielectric constant of silicon dioxide, and a metal material in contact with the first gate dielectric, the metal material being doped with an inert element. Integrated circuits including the transistors and methods of forming the transistors are also provided.

Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.

Abstract: Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing materials onto microfeature workpieces are disclosed herein. In one embodiment, a method includes depositing molecules of a gas onto a microfeature workpiece in the reaction chamber and selectively irradiating a first portion of the molecules on the microfeature workpiece in the reaction chamber with a selected radiation without irradiating a second portion of the molecules on the workpiece with the selected radiation. The first portion of the molecules can be irradiated to activate the portion of the molecules or desorb the portion of the molecules from the workpiece. The first portion of the molecules can be selectively irradiated by impinging the first portion of the molecules with a laser beam or other energy source.

Abstract: Methods for forming ruthenium films and semiconductor devices such as capacitors that include the films are provided.

Abstract: Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing materials onto microfeature workpieces are disclosed herein. In one embodiment, a method includes depositing molecules of a gas onto a microfeature workpiece in the reaction chamber and selectively irradiating a first portion of the molecules on the microfeature workpiece in the reaction chamber with a selected radiation without irradiating a second portion of the molecules on the workpiece with the selected radiation. The first portion of the molecules can be irradiated to activate the portion of the molecules or desorb the portion of the molecules from the workpiece. The first portion of the molecules can be selectively irradiated by impinging the first portion of the molecules with a laser beam or other energy source.

Abstract: Methods for forming ruthenium films and semiconductor devices such as capacitors that include the films are provided.

Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.

Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.

Abstract: There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content.

Abstract: Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a dielectric constant higher than a dielectric constant of silicon dioxide, and a metal material in contact with the first gate dielectric, the metal material being doped with an inert element. Integrated circuits including the transistors and methods of forming the transistors are also provided.

Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.