Abstract: An electrical antifuse bit cell structure includes a silicon controlled rectifier (SCR) having an anode, a cathode, and a blow gate. The blow gate is a Positive Field Effect Transistor (PFET) having a supply node for connection in series between a voltage supply and the anode of the SCR. The blow gate PFET in an on-state provides a permanent conductive path from the anode to the cathode.

Abstract: A semiconductor integrated circuit (IC) device includes a backside fuse structure and a backside contact. The backside fuse structure is located within the backside of the semiconductor IC device vertically between a transistor there above and a backside back end of the line (BEOL) network. The backside fuse structure includes a fuse wire and a deep via contact that is connected to both the fuse wire and to a frontside BEOL network. The backside contact is connected to the transistor, to the backside BEOL network, and to the fuse wire. The backside fuse structure may be in a non-programmed state or a programmed state. When in a non-programmed state, an open circuit exists that prevents current flow through the fuse wire or through the backside contact.

Abstract: A semiconductor integrated circuit (IC) device that includes a backside fuse structure. The backside fuse structure is located within the backside of the semiconductor IC device and may be vertically located between a microdevice and a backside back end of the line (BEOL) network. The backside fuse structure includes at least a fuse wire. The backside fuse structure may be in a non-programmed state or a programmed state. When in a non-programmed state, an open circuit exists that prevents current flow through the fuse wire. The backside fuse structure may be directly connected to a deep via contact and/or one or more conductive pathways within the backside BEOL network.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.

Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

Abstract: A system and method of operating a twin-transistor, multi-time programmable memory (MTPM) memory cell that ensures accurate reproducibility of bit values read after each of write cycle. Each multi-time programmable memory cell includes a series connection of a first transistor and a second transistor. The method includes writing, using a write circuit at select memory cell locations, initial bit values to one or more select memory cells. Then, using the write circuit, a rebalancing of a state of a parameter associated with one or more the first transistor or second transistor, at each the select memory cell, is performed. Then, an erasing cycle is performed, at each the rebalanced select memory cell, the written initial bit value. In one embodiment, the erasing cycle may first be performed prior to rebalancing. The rebalancing and erasing are to be performed prior to each bit value write cycle.

Abstract: The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse structure can include a metal dummy structure and an electrical fuse link substantially aligned with a portion of the metal dummy structure, wherein the metal dummy structure cools at least part of the electrical fuse link in response to an electric current passing through the electrical fuse link.

Abstract: The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse structure can include a metal dummy structure and an electrical fuse link substantially aligned with a portion of the metal dummy structure, wherein the metal dummy structure cools at least part of the electrical fuse link in response to an electric current passing through the electrical fuse link.

Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

Abstract: The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse structure can include a metal dummy structure and an electrical fuse link substantially aligned with a portion of the metal dummy structure, wherein the metal dummy structure cools at least part of the electrical fuse link in response to an electric current passing through the electrical fuse link.

Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.

Abstract: A method including forming a fuse link after a first fuse contact and a second fuse contact. The fuse link is in direct contact with both the first fuse contact and the second fuse contact. Embodiments of the invention provide an e-fuse that is capable of being connected to a device either through back end of line or by a long contact allowing for sufficient separation between the e-fuse and the device.

Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.

Abstract: A method including forming a fuse link after a first fuse contact and a second fuse contact. The fuse link is in direct contact with both the first fuse contact and the second fuse contact. Embodiments of the invention provide an e-fuse that is capable of being connected to a device either through back end of line or by a long contact allowing for sufficient separation between the e-fuse and the device.

Abstract: The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse structure can include a metal dummy structure and an electrical fuse link substantially aligned with a portion of the metal dummy structure, wherein the metal dummy structure cools at least part of the electrical fuse link in response to an electric current passing through the electrical fuse link.

Abstract: An electronic fuse structure including a first Mx metal comprising a conductive cap, an Mx+1 metal located above the Mx metal, wherein the Mx+1 metal does not comprise a conductive cap, and a via, wherein the via electrically connects the Mx metal to the Mx+1 metal in a vertical orientation.

Abstract: A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes an enhanced performance electrical fuse formed in a polysilicon fin using a trench silicide process. In one embodiment, at least one semiconductor fin is formed on a dielectric layer present on the surface of a semiconductor substrate. An isolation layer may be formed over the exposed portions of the dielectric layer and the at least one semiconductor fin. At least two contact vias may be formed through the isolation layer to expose the top surface of the semiconductor fin. A continuous silicide may be formed on and substantially below the exposed surfaces of the semiconductor fin extending laterally at least between the at least two contact vias to form an electronic fuse (eFuse). In another embodiment, the at least one semiconductor fin may be subjected to ion implantation to facilitate the formation of silicide.

Abstract: An embedded Multi-Time-Read-Only-Memory having a (MOSFET) cells' array having an initial threshold voltage (VT0) including the MOSFETs arranged in a row and column matrix, having gates in each row coupled to a wordline (WL) running in a first direction and sources in each one of the columns coupled to a bitline (BL) running in a second direction; creating two dimensional meshed source line network running in the first and second directions, in a standby state, wherein BLs and MSLN are at a voltage (VDD), and the WLs are at ground; storing a data bit by trapping charges in a dielectric of a target MOSFET, VT0 of target MOSFET increasing to another voltage (VT1) by a predetermined amount (?VT); reading a data bit by using the MOSFET threshold voltage having one of VT0 or VT1 to determine a trapped or de-trapped charge state, and resetting the data bit to a de-trapped state by de-trapping the charge.