Patents by Inventor Dan Moy
Dan Moy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11367734Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.Type: GrantFiled: February 4, 2020Date of Patent: June 21, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Faraz Khan, Dan Moy, Norman W. Robson, Robert Katz, Darren L. Anand, Toshiaki Kirihata
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Publication number: 20210242230Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.Type: ApplicationFiled: February 4, 2020Publication date: August 5, 2021Inventors: Faraz KHAN, Dan MOY, Norman W. ROBSON, Robert KATZ, Darren L. ANAND, Toshiaki KIRIHATA
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Patent number: 9893011Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.Type: GrantFiled: October 1, 2015Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Junjing Bao, Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Dan Moy, Andrew H. Simon
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Patent number: 9685404Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.Type: GrantFiled: January 11, 2012Date of Patent: June 20, 2017Assignee: International Business Machines CorporationInventors: Junjing Bao, Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald Filippi, Stephan Grunow, Naftali E. Lustig, Dan Moy, Andrew H. Simon
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Patent number: 9418745Abstract: A system and method of operating a twin-transistor, multi-time programmable memory (MTPM) memory cell that ensures accurate reproducibility of bit values read after each of write cycle. Each multi-time programmable memory cell includes a series connection of a first transistor and a second transistor. The method includes writing, using a write circuit at select memory cell locations, initial bit values to one or more select memory cells. Then, using the write circuit, a rebalancing of a state of a parameter associated with one or more the first transistor or second transistor, at each the select memory cell, is performed. Then, an erasing cycle is performed, at each the rebalanced select memory cell, the written initial bit value. In one embodiment, the erasing cycle may first be performed prior to rebalancing. The rebalancing and erasing are to be performed prior to each bit value write cycle.Type: GrantFiled: March 18, 2015Date of Patent: August 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Xiang Chen, Toshiaki Kirihata, Derek H. Leu, Dan Moy
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Patent number: 9337143Abstract: The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse structure can include a metal dummy structure and an electrical fuse link substantially aligned with a portion of the metal dummy structure, wherein the metal dummy structure cools at least part of the electrical fuse link in response to an electric current passing through the electrical fuse link.Type: GrantFiled: January 27, 2014Date of Patent: May 10, 2016Assignees: GlobalFoundries Inc., Samsung Electronics Co., Ltd., International Business Machines CorporationInventors: O Sung Kwon, Dan Moy, Kihwang Son, Xiaoqiang Zhang
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Patent number: 9337144Abstract: The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse structure can include a metal dummy structure and an electrical fuse link substantially aligned with a portion of the metal dummy structure, wherein the metal dummy structure cools at least part of the electrical fuse link in response to an electric current passing through the electrical fuse link.Type: GrantFiled: October 6, 2015Date of Patent: May 10, 2016Assignees: Samsung Electronics Co., LTD., International Business Machines Corporation, GlobalFoundries Inc.Inventors: O Sung Kwon, Dan Moy, Kihwang Son, Xiaoqiang Zhang
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Publication number: 20160027734Abstract: The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse structure can include a metal dummy structure and an electrical fuse link substantially aligned with a portion of the metal dummy structure, wherein the metal dummy structure cools at least part of the electrical fuse link in response to an electric current passing through the electrical fuse link.Type: ApplicationFiled: October 6, 2015Publication date: January 28, 2016Inventors: O Sung Kwon, Dan Moy, Kihwang Son, Xiaoqiang Zhang
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Publication number: 20160027733Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.Type: ApplicationFiled: October 1, 2015Publication date: January 28, 2016Inventors: Junjing Bao, Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Dan Moy, Andrew H. Simon
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Patent number: 9240406Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.Type: GrantFiled: April 21, 2014Date of Patent: January 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kai D. Feng, Dan Moy, Chengwen Pei, Robert R. Robison, Pinping Sun, Richard A. Wachnik, Ping-Chuan Wang
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Patent number: 9171800Abstract: A method including forming a fuse link after a first fuse contact and a second fuse contact. The fuse link is in direct contact with both the first fuse contact and the second fuse contact. Embodiments of the invention provide an e-fuse that is capable of being connected to a device either through back end of line or by a long contact allowing for sufficient separation between the e-fuse and the device.Type: GrantFiled: March 4, 2014Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Lawrence A. Clevenger, Zhengwen Li, Dan Moy, Viraj Y. Sardesai, Keith H. Tabakman
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Publication number: 20150303191Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.Type: ApplicationFiled: April 21, 2014Publication date: October 22, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai D. Feng, Dan Moy, Chengwen Pei, Robert R. Robison, Pinping Sun, Richard A. Wachnik, Ping-Chuan Wang
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Publication number: 20150255393Abstract: A method including forming a fuse link after a first fuse contact and a second fuse contact. The fuse link is in direct contact with both the first fuse contact and the second fuse contact. Embodiments of the invention provide an e-fuse that is capable of being connected to a device either through back end of line or by a long contact allowing for sufficient separation between the e-fuse and the device.Type: ApplicationFiled: March 4, 2014Publication date: September 10, 2015Applicant: International Business Machines CorporationInventors: Lawrence A. Clevenger, Zhengwen Li, Dan Moy, Viraj Y. Sardesai, Keith H. Tabakman
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Publication number: 20150214149Abstract: The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse structure can include a metal dummy structure and an electrical fuse link substantially aligned with a portion of the metal dummy structure, wherein the metal dummy structure cools at least part of the electrical fuse link in response to an electric current passing through the electrical fuse link.Type: ApplicationFiled: January 27, 2014Publication date: July 30, 2015Applicants: Internatioal Business Machines Corporation, Samsung Electronics Co., Ltd.Inventors: Dan Moy, Kwon O Sung, Kihwang Son, Xiaoqiang Zhang
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Patent number: 9064871Abstract: An electronic fuse structure including a first Mx metal comprising a conductive cap, an Mx+1 metal located above the Mx metal, wherein the Mx+1 metal does not comprise a conductive cap, and a via, wherein the via electrically connects the Mx metal to the Mx+1 metal in a vertical orientation.Type: GrantFiled: July 25, 2014Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: Junjing Bao, Elbert E. Huang, Yan Zun Li, Dan Moy
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Patent number: 9041151Abstract: A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes an enhanced performance electrical fuse formed in a polysilicon fin using a trench silicide process. In one embodiment, at least one semiconductor fin is formed on a dielectric layer present on the surface of a semiconductor substrate. An isolation layer may be formed over the exposed portions of the dielectric layer and the at least one semiconductor fin. At least two contact vias may be formed through the isolation layer to expose the top surface of the semiconductor fin. A continuous silicide may be formed on and substantially below the exposed surfaces of the semiconductor fin extending laterally at least between the at least two contact vias to form an electronic fuse (eFuse). In another embodiment, the at least one semiconductor fin may be subjected to ion implantation to facilitate the formation of silicide.Type: GrantFiled: May 31, 2013Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Christian Lavoie, Effendi Leobandung, Dan Moy
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Publication number: 20150138891Abstract: An embedded Multi-Time-Read-Only-Memory having a (MOSFET) cells' array having an initial threshold voltage (VT0) including the MOSFETs arranged in a row and column matrix, having gates in each row coupled to a wordline (WL) running in a first direction and sources in each one of the columns coupled to a bitline (BL) running in a second direction; creating two dimensional meshed source line network running in the first and second directions, in a standby state, wherein BLs and MSLN are at a voltage (VDD), and the WLs are at ground; storing a data bit by trapping charges in a dielectric of a target MOSFET, VT0 of target MOSFET increasing to another voltage (VT1) by a predetermined amount (?VT); reading a data bit by using the MOSFET threshold voltage having one of VT0 or VT1 to determine a trapped or de-trapped charge state, and resetting the data bit to a de-trapped state by de-trapping the charge.Type: ApplicationFiled: November 20, 2013Publication date: May 21, 2015Applicant: International Business Machiness CorporationInventors: Subramanian S. Iyer, Toshiaki Kirihata, Chandrasekharan Kothandaraman, Derek H. Leu, Dan Moy
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Patent number: 9025386Abstract: An embedded Multi-Time-Read-Only-Memory having a (MOSFET) cells' array having an initial threshold voltage (VT0) including the MOSFETs arranged in a row and column matrix, having gates in each row coupled to a wordline (WL) running in a first direction and sources in each one of the columns coupled to a bitline (BL) running in a second direction; creating two dimensional meshed source line network running in the first and second directions, in a standby state, wherein BLs and MSLN are at a voltage (VDD), and the WLs are at ground; storing a data bit by trapping charges in a dielectric of a target MOSFET, VT0 of target MOSFET increasing to another voltage (VT1) by a predetermined amount (?VT); reading a data bit by using the MOSFET threshold voltage having one of VT0 or VT1 to determine a trapped or de-trapped charge state, and resetting the data bit to a de-trapped state by de-trapping the charge.Type: GrantFiled: November 20, 2013Date of Patent: May 5, 2015Assignee: International Business Machines CorporationInventors: Subramanian S. Iyer, Toshiaki Kirihata, Chandrasekharan Kothandaraman, Derek H. Leu, Dan Moy
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Publication number: 20140353796Abstract: A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes an enhanced performance electrical fuse formed in a polysilicon fin using a trench silicide process. In one embodiment, at least one semiconductor fin is formed on a dielectric layer present on the surface of a semiconductor substrate. An isolation layer may be formed over the exposed portions of the dielectric layer and the at least one semiconductor fin. At least two contact vias may be formed through the isolation layer to expose the top surface of the semiconductor fin. A continuous silicide may be formed on and substantially below the exposed surfaces of the semiconductor fin extending laterally at least between the at least two contact vias to form an electronic fuse (eFuse). In another embodiment, the at least one semiconductor fin may be subjected to ion implantation to facilitate the formation of silicide.Type: ApplicationFiled: May 31, 2013Publication date: December 4, 2014Inventors: Christian Lavoie, Effendi Leobandung, Dan Moy
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Publication number: 20140332856Abstract: An electronic fuse structure including a first Mx metal comprising a conductive cap, an Mx+1 metal located above the Mx metal, wherein the Mx+1 metal does not comprise a conductive cap, and a via, wherein the via electrically connects the Mx metal to the Mx+1 metal in a vertical orientation.Type: ApplicationFiled: July 25, 2014Publication date: November 13, 2014Inventors: Junjing Bao, Elbert E. Huang, Yan Zun Li, Dan Moy