Patents by Inventor Dan Moy
Dan Moy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080089159Abstract: An apparatus and method for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.Type: ApplicationFiled: October 11, 2006Publication date: April 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan Moy, Stephen Wu, Peter Wang, Brian W. Messenger, Edwin Soler, Gabriel Chiulli
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Publication number: 20050003626Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.Type: ApplicationFiled: July 22, 2004Publication date: January 6, 2005Inventors: Stephen Fox, Neena Garg, Kenneth Giewont, Junedong Lee, Siegfried Maurer, Dan Moy, Maurice Norcott, Devendra Sadana
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Patent number: 6784072Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.Type: GrantFiled: July 22, 2002Date of Patent: August 31, 2004Assignee: International Business Machines CorporationInventors: Stephen Richard Fox, Neena Garg, Kenneth John Giewont, Junedong Lee, Siegfried Lutz Maurer, Dan Moy, Maurice Heathcote Norcott, Devendra Kumar Sadana
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Patent number: 6713791Abstract: A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc.Type: GrantFiled: January 26, 2001Date of Patent: March 30, 2004Assignee: IBM CorporationInventors: Louis L. Hsu, Rajiv V. Joshi, Fariborz Assaderaghi, Dan Moy, Werner Rausch, James Culp
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Publication number: 20040013886Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.Type: ApplicationFiled: July 22, 2002Publication date: January 22, 2004Applicant: International Business Machines CorporationInventors: Stephen Richard Fox, Neena Garg, Kenneth John Giewont, Junedong Lee, Siegfried Lutz Maurer, Dan Moy, Maurice Heathcote Norcott, Devendra Kumar Sadana
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Patent number: 6635543Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.Type: GrantFiled: December 31, 2002Date of Patent: October 21, 2003Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Jack A. Mandelman, Dan Moy, Byeongju Park, William R. Tonti
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Publication number: 20030104658Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.Type: ApplicationFiled: December 31, 2002Publication date: June 5, 2003Inventors: Toshiharu Furukawa, Jack A. Mandelman, Dan Moy, Byeongju Park, William R. Tonti
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Patent number: 6566177Abstract: A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench.Type: GrantFiled: October 25, 1999Date of Patent: May 20, 2003Assignee: International Business Machines CorporationInventors: Carl J. Radens, Gary B. Bronner, Tze-chiang Chen, Bijan Davari, Jack A. Mandelman, Dan Moy, Devendra K. Sadana, Ghavam Ghavami Shahidi, Scott R. Stiffler
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Patent number: 6555891Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.Type: GrantFiled: October 17, 2000Date of Patent: April 29, 2003Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Jack A. Mandelman, Dan Moy, Byeongju Park, William R. Tonti
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Patent number: 6538299Abstract: A semiconductor device (and method for forming the device) includes a silicon-on-insulator (SOI) wafer formed on a substrate surface. An isolation trench in the wafer surface surrounds alternating p-type trenches and n-type trenches and electrically isolates the device from the substrate, thereby allowing the device to be effectively utilized as a differential detector in an optoelectronic circuit.Type: GrantFiled: October 3, 2000Date of Patent: March 25, 2003Assignee: International Business Machines CorporationInventors: Young H. Kwark, Dan Moy, Mark B. Ritter, Dennis L. Rogers, Jeffrey J. Welser
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Publication number: 20020100918Abstract: A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc.Type: ApplicationFiled: January 26, 2001Publication date: August 1, 2002Inventors: Louis L. Hsu, Rajiv V. Joshi, Fariborz Assaderaghi, Dan Moy, Werner Rausch, James Culp
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Patent number: 6426252Abstract: A silicon on insulator (SOI) dynamic random access memory (DRAM) cell, array and method of manufacture. The memory cell includes a vertical access transistor above a trench storage capacitor in a layered wafer. A buried oxide (BOX) layer formed in a silicon wafer isolates an SOI layer from a silicon substrate. Deep trenches are etched through the upper surface SOI layer, the BOX layer and into the substrate. Each trench capacitor is formed in the substrate and, the access transistor is formed on a sidewall of the SOI layer. Recesses are formed in the BOX layer at the SOI layer. A polysilicon strap recessed in the BOX layer connects each polysilicon storage capacitor plate to a self-aligned contact at the source of the access transistor. Dopant is implanted into the wafer to define device regions. Access transistor gates are formed along the SOI layer sidewalls. Shallow trenches are formed and filled with insulating material to isolate cells from adjacent cells.Type: GrantFiled: October 25, 1999Date of Patent: July 30, 2002Assignee: International Business Machines CorporationInventors: Carl J. Radens, Gary B. Bronner, Tze-chiang Chen, Bijan Davari, Jack A. Mandelman, Dan Moy, Devendra K. Sadana, Ghavam Ghavami Shahidi, Scott R. Stiffler
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Patent number: 5418188Abstract: A method for controlled positioning of a compound layer such as TiSi.sub.2 or CoSi.sub.2 in a multilayer device such as a semiconductor is disclosed. The compound surface layer is situated adjacent to an intermediate layer comprised of one of the two types of atoms present in the molecules of the adjacent compound surface layer. The intermediate layer is also situated adjacent to a base layer, such as a semiconductor substrate. An epitaxial silicon layer is the suggested intermediate layer where the surface layer is comprised of TiSi.sub.2 or CoSi.sub.2. By simultaneously heating the multilayer device and using an appropriate etching process for selectively removing the atoms from the surface of the compound surface layer which are common in both the compound and intermediate layer (i.e., silicon) the intermediate layer can be reduced in thickness and/or fully consumed while the structural integrity of the compound surface layer remains essentially unchanged.Type: GrantFiled: September 5, 1991Date of Patent: May 23, 1995Assignee: International Business Machines CorporationInventors: James M. E. Harper, Dan Moy, Shahrnaz Motakef
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Patent number: 5221853Abstract: Selective deposition of a refractory metal on a silicon substrate utilizing high temperatures and a silane reduction process in which the flow rate ratio of silane to refractory metal halide gas is less than one. In a second embodiment, an additional layer of the refractory metal is deposited utilizing a hydrogen reduction of the metal halide gas at very high temperatures. In both embodiments, a refractory metal barrier layer may be provided by forming a self-aligned refractory metal silicide layer. Alternatively, a two layer self-aligned barrier is formed of a refractory metal silicide lower layer and a refractory metal nitride upper layer and the refractory metal is selectively deposited on the metal nitride.Type: GrantFiled: September 20, 1991Date of Patent: June 22, 1993Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Choon-Sik Oh, Dan Moy
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Patent number: 5202287Abstract: Selective deposition of a refractory metal on a silicon substrate utilizing high temperatures and a silane reduction process in which the flow rate ratio of silane to refractory metal halide gas is less than one. In a second embodiment, an additional layer of the refractory metal is deposited utilizing a hydrogen reduction of the metal halide gas at very high temperatures. In both embodiments, a refractory metal barrier layer may be provided by forming a self-aligned refractory metal silicide layer. Alternatively, a two layer self-aligned barrier is formed of a refractory metal silicide lower layer and a refractory metal nitride upper layer and the refractory metal is selectively deposited on the metal nitride.Type: GrantFiled: January 6, 1992Date of Patent: April 13, 1993Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Choon-Sik Oh, Dan Moy
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Method for selective deposition of refractory metals on silicon substrates and device formed thereby
Patent number: 5084417Abstract: Selective deposition of a refractory metal on a silicon substrate utilizing high temperature and a silane reduction process in which the flow rate ratio of silane to refractory metal halide gas is less than one. In a second embodiment, an additional layer of the refractory metal is deposited utilizing a hydrogen reduction of the metal halide gas at very high temperatures. In both embodiments, a refractory metal barrier layer may be provided by forming a self-aligned refractory metal silicide layer. Alternatively, a two layer self-aligned barrier is formed of a refractory metal silicide lower layer and a refractory metal nitride upper layer and the refractory metal is selectively deposited on the metal nitride.Type: GrantFiled: March 13, 1989Date of Patent: January 28, 1992Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Choon-Sik Oh, Dan Moy -
Patent number: 4974056Abstract: A gate structure for integrated circuit devices which includes a work function layer, a low resistivity layer, and an electrically conductive barrier layer between the two other layers to prevent the other two layers from intermixing. The work function controlling layer is preferably selected from the group of tungsten, molybdenum, their silicides, or a combination thereof.Type: GrantFiled: May 22, 1987Date of Patent: November 27, 1990Assignee: International Business Machines CorporationInventors: Stephen B. Brodsky, Dan Moy, Rajiv V. Joshi