Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.

Abstract: The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.

Abstract: Memory devices and methods include receiving data at an input buffer and outputting serial data. The serial shift data is passed toward a serial shift register that shifts its stored data into a data write bus in a parallel format. Serial shift register loading circuitry controls loading of a serial shift register. The serial shift register loading circuitry is configured to receive a data strobe signal and provide the data strobe to the serial shift register to cause the serial shift register to shift in the serial data during a write operation. The serial register loading circuitry includes gating circuitry that is configured to cutoff provision of the data strobe from the serial register loading circuitry based at least in part on a load signal that indicates that the data write bus has been loaded with the serial data in a parallel format.

Abstract: Memory device and methods for controlling the memory device include an input buffer of the memory device receives input data from external to the memory device and outputs serial data. A serial shift register that shifts in the serial data and to output the serial data in a parallel format as parallel data. A parallel register that receives the parallel data from the serial shift register and buffered data directly from the input buffer. The parallel register that passes the parallel data and the buffered data to a data write bus to be stored memory banks of the memory device. Serial-to-parallel conversion circuitry controls loading of the parallel register from the serial shift register and the input buffer. The serial-to-parallel conversion circuitry utilizes a first loading signal to load the buffered data into the parallel register and a second loading signal to load the parallel data into the parallel register.

Abstract: Techniques provided herein compensate for an internal and external timing skew between a data strobe (DQS) and a clock (CLK), by: executing at least one write leveling initialization procedure (WLInit) that uses a mode-register-write (MRW) command to synchronize a timing between a data strobe (DQS) with a clock (CLK) based upon capture of an internal write command. Internal and external timing skew is identified based upon the WLInit. The internal timing skew is skew caused internal to a memory device and the external timing skew is skew caused external to the memory device. A timing between the DQS and the CLK is adjusted based upon the internal and external timing skew.

Abstract: Memory device and methods for controlling the memory device include an input buffer of the memory device receives input data from external to the memory device and outputs serial data. A serial shift register that shifts in the serial data and to output the serial data in a parallel format as parallel data. A parallel register that receives the parallel data from the serial shift register and buffered data directly from the input buffer. The parallel register that passes the parallel data and the buffered data to a data write bus to be stored memory banks of the memory device. Serial-to-parallel conversion circuitry controls loading of the parallel register from the serial shift register and the input buffer. The serial-to-parallel conversion circuitry utilizes a first loading signal to load the buffered data into the parallel register and a second loading signal to load the parallel data into the parallel register.

Abstract: Memory devices coupled to host devices may receive clocking signals and data strobe signals during write operations, which may present a skew. Memory specifications may include Write Preambles, preambles in the data signal provided at the beginning of write operations. Memory devices that decode particular features in the preamble, and that may relax the skew tolerances are provided. The memory devices may include configurable decoders that may be adjusted based on the features in the preamble or the preamble type. For example, memory devices may employ a rising edge, a falling edge, a low level, or a high level based on the specific type of preamble. Skew tolerances between the clock and the data strobe signals may be further improved by employing early write command launch points, using a training mechanism.

Abstract: Methods and systems for internal timing schemes are provided. A data strobe (DQS) signal is received at a memory device. The DQS signal is shifted in a negative direction relative to a clock of the memory device to cause a fail point of a flip flop of the memory device. After causing the fail point, the DQS signal is shifted in a positive direction relative to the clock. A transition edge of an internal write signal (IWS) is centered in a DQS period, such as a write preamble. The IWS indicates that a write command is to be captured. Moreover, centering the transition edge includes selectively delaying the IWS in the negative direction.

Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.

Abstract: Methods and systems for internal timing schemes are provided. A data strobe (DQS) signal is received at a memory device. The DQS signal is shifted in a negative direction relative to a clock of the memory device to cause a fail point of a flip flop of the memory device. After causing the fail point, the DQS signal is shifted in a positive direction relative to the clock. A transition edge of an internal write signal (IWS) is centered in a DQS period, such as a write preamble. The IWS indicates that a write command is to be captured. Moreover, centering the transition edge includes selectively delaying the IWS in the negative direction.

Abstract: A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals based. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.

Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.

Abstract: Memory devices coupled to host devices may receive clocking signals and data strobe signals during write operations, which may present a skew. Memory specifications may include Write Preambles, preambles in the data signal provided at the beginning of write operations. Memory devices that decode particular features in the preamble, and that may relax the skew tolerances are provided. The memory devices may include configurable decoders that may be adjusted based on the features in the preamble or the preamble type. For example, memory devices may employ a rising edge, a falling edge, a low level, or a high level based on the specific type of preamble. Skew tolerances between the clock and the data strobe signals may be further improved by employing early write command launch points, using a training mechanism.

Abstract: Methods and systems that may employ adjustments to the latencies in the input circuitry to reduce the latency during initialization period and to prevent undesired effects from metastability are provided. Disclosed systems may employ adjustable delays during a signal training process to cause adjustments in the timing of the host that will reduce latencies during write cycles. Certain systems may further reduce latencies by employing input logic circuitry that produces a valid, consistent signal from the bidirectional connection, such as a gate, and preventing metastability in input circuitry altogether. Such circuitry allows bypassing of initialization periods to stabilize the input, and allows further reduction of the initialization.

Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.

Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.

Abstract: Methods and systems that may employ adjustments to the latencies in the input circuitry to reduce the latency during initialization period and to prevent undesired effects from metastability are provided. Disclosed systems may employ adjustable delays during a signal training process to cause adjustments in the timing of the host that will reduce latencies during write cycles. Certain systems may further reduce latencies by employing input logic circuitry that produces a valid, consistent signal from the bidirectional connection, such as a gate, and preventing metastability in input circuitry altogether. Such circuitry allows bypassing of initialization periods to stabilize the input, and allows further reduction of the initialization.

Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.