Abstract: A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

Abstract: Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM), An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses, Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; adaptive initial erasing voltages; and single- and hybrid-phase algorithms with sector to sector estimation of erase characteristics by table lookup. Techniques are also employed for controlling the uniformity of program/erase cycling of cells in each erasable unit group, Defects handling includes an adaptive data encoding scheme.

Abstract: A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

Abstract: A semiconductor integrated circuit device is disclosed having first and second conducting layers, with the first layer having a shape which enhances field emission tunneling off of the surface thereof. A dual thickness dielectric layer separates the conducting layers. When a potential difference is applied between the conducting layers, field emission tunneling occurs primarily through the thinner portion of the dielectric layer.

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract: Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM). An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses. Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; adaptive initial erasing voltages; and single-and hybrid-phase algorithms with sector to sector estimation of erase characteristics by table lookup. Techniques are also employed for controlling the uniformity of program/erase cycling of cells in each erasable unit group. Defects handling includes an adaptive data encoding scheme.

Abstract: A semiconductor integrated circuit device is disclosed having first and second conducting layers, with the first layer having a shape which enhances field emission tunneling off of the surface thereof. A dual thickness dielectric layer separates the conducting layers. When a potential difference is applied between the conducting layers, field emission tunneling occurs primarily through the thinner portion of the dielectric layer.

Abstract: A nonvolatile, semiconductor randon access memory cell comprising a static RAM element and a nonvolatile memory element having differential charge storage capabilities is presented. The static RAM and nonvolatile memory elements are interconnected to allow information to be exchanged between two elements, thus allowing the faster static RAM element to serve as the primary memory to the system and allowing the nonvolatile memory element to serve as permanent storage during power-down conditions. In one embodiment, the nonvolatile memory element comprises two electrically erasable PROM devices (EEPROMs). The two EEPROM devices store differential charges corresponding to the complementary outputs of the static RAM element. The nature of the differential charge storage allows lower programming voltages to be used on the EEPROM devices, resulting in increased storage intergrity and increased endurance of the EEPROM devices.

Abstract: A compact, floating gate, nonvolatile, electrically alterable memory device is fabricated with three layers of polysilicon. In a nonvolatile memory array, each cell is electrically isolated from other cells to eliminate data disturb conditions in nonaddressed cells of the memory array. The memory cell and array is described as including four electrode layers, one of which being formed as a substrate coupling electrode. The cell is also described as being relatively process intolerant. The first electrode layer above the substrate is used to mask the diffusion or implantation of the substrate coupling electrode and other regions in the substrate to form self-aligned active devices.

Abstract: A simple, compact voltage reference circuit for an NMOS integrated circuit comprises a series connected depletion transistor with its gate at ground and an enhancement transistor with its gate connected to an output node between the two transistors.

Abstract: A compact, floating gate, nonvolatile, electrically alterable memory device is fabricated with three layers of polysilicon. In a nonvolatile memory array, each cell is electrically isolated from other cells to eliminate data disturb conditions in nonaddressed cells of the memory array. The memory cell and array is described in a first embodiment as including four electrode layers, one of which being formed as a substrate coupling electrode. A second embodiment includes a three electrode layer device wherein the need for the substrate coupling electrode is eliminated.

Abstract: A nonvolatile memory cell (16) is fabricated on a substrate (12) and includes a source region (46) and drain regions (48, 50 and 52). Step oxides (40, 42 and 44) are fabricated respectively over the regions (46, 48 and 52). A gate oxide (58) is formed between the step oxides (40 and 42). A thin oxide tunneling element (74) is fabricated between the step oxides (42, 44) and over the drain region (50). A floating gate (38) comprising a polysilicon layer is fabricated over the step oxides (40, 42, 44), the gate oxide (58) and the tunneling element (74). An insulation layer (36) is fabricated over the floating gate (38). Finally, a control gate (34) is fabricated over the insulating layer (36) to provide capacitive coupling to the floating gate (38).

Abstract: A compact memory cell combines a volatile dynamic storage section with a shadow nonvolatile section in two vertically stacked element arrays.

Abstract: An electrically erasable programmable read only memory employs a single unsteered on-chip high voltage generator that applies high voltage simultaneously to all cells on the chip.

Abstract: A nonvolatile random access memory cell (10) includes a static random access memory circuit and a corresponding nonvolatile memory circuit. The volatile memory circuit operates in a conventional manner and has first and second data states. Upon receipt of a store command signal a charge storage node is driven to either a first or a second charge state, depending upon the data state in the volatile memory circuit. For one charge state the charge storage signal is gated through a transistor (64) and a capacitor (68) to a floating gate node (44). Charge is transferred to and from the floating gate node (44) through current tunneling elements (48,50) which comprise a dielectric fabricated on a monocrystalline substrate. For the recall operation a recall command signal is applied to a transistor (52) which couples a transistor (42) to the DATA node (22) of the volatile memory circuit.

Abstract: A user-programmable and reprogrammable programmed logic array includes a self-indexing pointer to direct successive input signals to the proper cell within the array. A particular application is that of a ROM patch to correct coding errors in a ROM.

Abstract: An electrically programmable read only memory (EPROM) of the floating gate type is constructed having an improved coupling ratio made by allowing the edges of the floating gates to be self aligned with the edges of the control gates. The ratio of the capacitance between the floating gate and control gate is increased by extending the floating gate out over the source and drain.

Abstract: A nonvolatile static random access memory cell (10) for storing data in a nonvolative state and recalling the data in its true state is disclosed. Cross-coupled transistors (12, 14) are provided having respective first and second nodes (16, 18) which are maintained at complementary logic states for volatile data storage. At least one tunnel capacitor (34), each having a floating node (36) is operatively coupled to the gate and drain terminals of one of said cross-coupled transistors (12, 14). At least one switch transistor (48) is operatively coupled to one of the first and second nodes (16, 18) and to one tunnel capacitor floating node (36). The at least one tunnel capacitor (34) and the at least one switch transistor (48) operatively coact for nonvolatile saving of volatile data stored in the cross-coupled transistors (12, 14), for recalling nonvolatile stored data in its true state to the cross-coupled transistors (12, 14), by the capacitive imbalance on the first and second nodes (16, 18).

Abstract: Polycrystalline silicon resistor elements are formed in MOS integrated circuits by a method which requires no additional mask and etch steps other than a standard double-level poly process. The resistors are defined in first level polysilicon which also forms floating gates in FAMOS devices. The resistors are masked by the second level poly which is patterned to define control gates for the FAMOS cells at the same time as the resistor mask is created. The first level poly is implanted at a level which produces the desired resistivity, which is same as the necessary doping level for the floating gates. FAMOS cells are floating gate MOS transistors which are electrically programmable and may also be electrically erasable or electrically alterable.

Abstract: An electrically programmable memory array of the floating gate type with a high coupling ratio is made by a process which allows the edges of the floating gates to be self-aligned with the edges of the control gates. The source and drain regions are formed prior to applying the first level polysilicon by a process which leaves these regions covered with thick oxide, rather than using the polysilicon as a mask to define the gate areas. The ratio of the capacitance between the floating gate and control gate to the total capacitance at the floating gate is increased by extending the floating gate out over the source and drain since the thick oxide reduces coupling from the floating gate to the source and drain.