Abstract: A semiconductor device may comprise an insulator substrate, a second substrate, a first structured metallization layer comprising a first section configured to operate at a first potential, and a second section configured to operate at a second potential. The insulator substrate may comprise a second structured metallization layer which may comprise a first section coupled to the first potential and a second section coupled to the second potential. At least one routable third structured metallization layer may comprise a first segment coupled to the second potential and a second segment coupled to the first potential.

Abstract: A transistor module, driver for transistor module, corresponding system and method are provided. The transistor module comprises a transistor, an overcurrent protection circuit configured to detect an overcurrent condition of the transistor and to set the transistor to an overcurrent protection state in response to detecting the overcurrent condition, and a signaling circuit coupled to a control terminal of the transistor module and configured to modify a signal level at the control terminal in response to the overcurrent protection circuit detecting the overcurrent condition.

Abstract: An electronic device includes an interface configured to receive telemetry information for one or more power semiconductor devices and a data acquisition and processing unit. The data acquisition and processing unit may be configured to increase a gate voltage above a maximum permitted level for each of the one or more power semiconductor devices having a current slew rate that exceeds a predetermined level as determined by the telemetry information. The data acquisition and processing unit may be configured to increase a gate voltage above a maximum permitted level for each of the one or more power semiconductor devices having a temperature that exceeds a predetermined level as determined by the telemetry information. An electronic system that includes the electronic device is also described.

Abstract: A circuit includes an input node configured to receive a gate control signal for controlling a dual gate transistor arrangement, a first output node configured to be coupled to a first gate node of the dual gate transistor arrangement, a first switch coupled between the input node and the first output node, and a second output node configured to be coupled to a second gate node of the dual gate transistor arrangement and coupled to the input node. A control circuit is configured to, upon detecting that the gate control signal indicates a turn-off of the dual gate transistor arrangement, open the first switch for a first predefined time period, and close the first switch after the first predefined time period.

Abstract: Switch modules, driver circuits for switch modules and corresponding methods are provided. In an implementation, a switch module includes a transistor switch and a short circuit detection circuit. The transistor switch includes a control terminal, a first load terminal and a second load terminal. The short circuit detection circuit is configured to detect a short circuit state between the first load terminal and the second load terminal and to automatically switch off the transistor switch without additional signaling, by automatically electrically coupling the control terminal to the first load terminal in response to detecting the short circuit state. The short circuit detection circuit is energized by a voltage between the control terminal and the first load terminal.

Abstract: Switch modules, driver circuits for switch modules and corresponding methods are provided. In an implementation, a switch module includes a transistor switch including a control terminal, a first load terminal and a second load terminal, and a short circuit detection circuit configured to detect a short circuit state between the first load terminal and the second load terminal and to electrically couple the control terminal and the first load terminal in response to detecting the short circuit state. The short circuit detection circuit is supplied by a voltage between the control terminal and the first load terminal.

Abstract: A switching assembly includes a common gate structure. A first transistor includes a first gate terminal. A second transistor includes a second gate terminal. A first coil is electrically connected between the first gate terminal and the common gate structure. A second coil is electrically connected between the second gate terminal and the common gate structure. The first coil and the second coil are inversely inductively coupled with reference to a current supplied through the common gate structure.

Abstract: A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to control a gate voltage to generate an on-current during a plurality of turn-on switching events to turn on the transistor. The gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage, and a second driver configured to, during a boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage. A control circuit measures a transistor parameter representative of a reverse recovery current of the transistor for a turn-on switching event during which the transistor is transitioned to an on state and controls the first driver and controls the second driver based on the measured transistor parameter.

Abstract: A semiconductor arrangement includes at least two switching devices of a first type electrically coupled in parallel between first and second terminals, and at least two switching devices of a second type electrically coupled in parallel between the second terminal and a third terminal. One first diode is electrically coupled in parallel to each switching device of the first type. One second diode is electrically coupled in parallel to each switching device of the second type. The switching devices are arranged in a power semiconductor module having first and second longitudinal sides and first and second narrow sides. The first type switching devices and first diodes are arranged alternatingly in one row along the first longitudinal side. The second type switching devices and second diodes are arranged alternatingly in another row along the second longitudinal side. An axis of symmetry that extends perpendicular to the first and second narrow sides.

Abstract: A semiconductor module arrangement includes a housing, a first semiconductor substrate arranged inside the housing, a second semiconductor substrate arranged inside the housing, a first plurality of controllable semiconductor elements, and a second plurality of controllable semiconductor elements. During operation of the semiconductor module arrangement, each controllable semiconductor element of the first plurality of controllable semiconductor elements generates switching losses and conduction losses, the switching losses being greater than the conduction losses. Further during operation of the semiconductor module arrangement, each controllable semiconductor element of the second plurality of controllable semiconductor elements generates switching losses and conduction losses, the conduction losses being greater than the switching losses.

Abstract: An electronic device includes an interface configured to receive telemetry information for one or more power semiconductor devices and a data acquisition and processing unit. The data acquisition and processing unit may be configured to increase a gate voltage above a maximum permitted level for each of the one or more power semiconductor devices having a current slew rate that exceeds a predetermined level as determined by the telemetry information. The data acquisition and processing unit may be configured to increase a gate voltage above a maximum permitted level for each of the one or more power semiconductor devices having a temperature that exceeds a predetermined level as determined by the telemetry information. An electronic system that includes the electronic device is also described.

Abstract: A method of monitoring a thermal impedance of at least a portion of a thermal path between a semiconductor device having at least two output terminals and a heat sink s provided. The method includes causing power dissipation in the semiconductor device by reloading parasitic capacitances of the semiconductor device such that the at least two output terminals are at the same voltage level, measuring a first temperature in response to the power dissipation at a first end of the portion of the thermal path, measuring a second temperature in response to the power dissipation at a second end of the portion of the thermal path, and determining a measure of the thermal impedance based on the first temperature and the second temperature.

Abstract: An electronic device includes: an interface configured to receive telemetry information for one or more power semiconductor devices; and a data acquisition and processing unit. The data acquisition and processing unit may be configured to periodically update an estimate of a remaining lifetime of the one or more power semiconductor devices, based on the telemetry information collected during use of the one or more power semiconductor devices and received at the interface. The data acquisition and processing unit may be configured to adjust one or more operating parameters for each of the one or more power semiconductor devices that has reached a predetermined level of degradation as determined by the telemetry information. An electronic system that includes the electronic device is also described.

Abstract: An electronic device includes: an interface configured to receive telemetry information for one or more power semiconductor devices; and a data acquisition and processing unit. The data acquisition and processing unit may be configured to periodically update an estimate of a remaining lifetime of the one or more power semiconductor devices, based on the telemetry information collected during use of the one or more power semiconductor devices and received at the interface. The data acquisition and processing unit may be configured to adjust one or more operating parameters for each of the one or more power semiconductor devices that has reached a predetermined level of degradation as determined by the telemetry information. An electronic system that includes the electronic device is also described.

Abstract: A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

Abstract: A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to control a gate voltage to generate an on-current during a plurality of turn-on switching events to turn on the transistor. The gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage, and a second driver configured to, during a boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage. A control circuit measures a transistor parameter representative of a reverse recovery current of the transistor for a turn-on switching event during which the transistor is transitioned to an on state and controls the first driver and controls the second driver based on the measured transistor parameter.

Abstract: A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to generate an on-current during a plurality of turn-on switching events to turn on the transistor, wherein the gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage and a second driver configured to, during a first boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage; a measurement circuit configured to measure a transistor parameter indicative of an oscillation of a load current for a turn-on switching event; and a controller configured to receive the measured transistor parameter and regulate a length of the first boost interval based on the measured transistor parameter.

Abstract: A semiconductor assembly includes a semiconductor switching device, a conductive load base structure, and a current sense unit. The semiconductor switching device includes a drain structure and one or more array units, wherein each array unit includes a load pad and a plurality of transistor cells electrically connected in parallel between the load pad of the array unit and the drain structure. The current sense unit is electrically connected between a first one of the load pads and the load base structure.

Abstract: A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

Abstract: A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor that are switched in a complementary manner. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.