Abstract: A parcel mailing system includes a postage value determining scale and peripheral mailing system devices such as a postage meter/mailing machine. The scale includes a main processor, a memory which stores postage rate data, a weighing device which generates weight indicative signals, a display, and a keyboard. A voice recognition subsystem is coupled to the system processor for hands free operator entry of information relating to postage value determinations. The voice recognition subsystem is trained to recognize various operator words and generate appropriate signals for postage value determination, e.g. zone information, zip code information, and rate classifications, as well as command signals. The system processor receives such signals from either the voice recognition subsystem or the keyboard.

Abstract: A postage value computing system includes both apparatus and a method for determining the postage of an article to be mailed for various domestic and international classes of postal service. Postal information such as carrier type, class and destination data are introduced into the system and used to access a memory which stores common structured rate data. Major rate structures are defined by weight headers which specify the upper and lower limits of weight ranges and the weight increments within those ranges. To minimize memory requirements, foreign countries are grouped as a function of such common structured rate data including permissible weight limits. Memory space is conserved through the utilization of a common postage computation routine including various equation subroutines for generating requisite postage values in accordance with the retrieved postage rate data.

Abstract: An improved electronic mailing apparatus and method is disclosed which provides customized zip to zone data reflecting variations in postal cost for a particular class of postal service. The apparatus includes a first memory means for storing standard zip to zone conversion data for existing, standard zip to zone conversion tables. A second memory means is provided for storing custom zip to zone conversion data for only a limited number of conversion tables. The custom data reflects postal cost variations in a particular class. A manually actuated switching means is provided for selectively addressing a memory sector of the second memory means. This sector stores custom conversion data for zip to zone conversion table corresponding to the zip code area where the meter is located. Memory requirements for custom data storage are thereby substantially reduced.

Abstract: Automatic postage value computing for individually selected services is described using a replaceable individualized directory memory and a replaceable rate chart memory suitable with all directory memories. Memories are provided with pseudo rate charts that resemble conventional rate charts but serve to either grant or deny access to a rate chart depending upon the user's selection. The use of pseudo rate charts permits an unbundling of the postage value computation services to serve the user's needs, without requiring program changes. With individualized directory memory rate selection the updating of user rate chart memories is limited to those rates he has selected. Several embodiments are described.

Abstract: A method and apparatus are described for controlling access of a user of a postal value computing system to the computation of special fees. A directory memory stores a special fee control byte which is combined with a rate fee screen byte that is generated by the system to represent the special fee computations requested in response to actuation of the keyboard. The combining of the bytes employs a bit for bit AND operation with the result stored as a modified rate screen byte for use in the subsequent special fee computations. Access may then be granted or denied, depending upon the special fee control byte.

Abstract: An interface between a system processor of an automated mailing system and selected peripheral devices carries peripheral support hardware and software for communication with the peripherals. The interface includes a board having a memory wherein programs for formatting communications with the peripherals are stored. A working memory for the temporary storage of commands and data for communication to the peripherals and a peripheral controller for establishing a communications link with a selected peripheral are also carried on the interface board. The inclusion of additional peripheral devices or the substitution of alternate peripheral devices which would require revision of communications formatting programs does not require reprogramming of the system processor and is accommodated by revising the program stored in the interface program memory.

Abstract: A postage value determining scale includes a processor which accesses postage data stored in a rate PROM carried on a card. In a basic implementation, the PROM card is mounted to a memory port socket of a circuit board which carries the processor. The processor is programmed for optional postage value related functions such as zip code to destination zone conversions and postage rate determinations for mailing from a remote origination point. The PROM carried on the rate PROM card has insufficient memory space for the optional functions. When a scale capable of providing the optional features is desired, in lieu of connecting the rate PROM card directly to the memory port, a transition board is provided for connecting the main board to a ribbon cable assembly. The ribbon cable is connected, at its opposite end, to a carrier board having a plurality of sockets and a cage for mounting a plurality of memory carrying cards including the rate PROM card.

Abstract: An automated mailing system includes a postage value determining system processor, a scale for providing weight indicative signals, a keyboard for operator entry of information relating to a determination of postage, and a plurality of peripheral devices. A peripheral controller interface establishes communications links with the peripheral devices. An incompatible systems interface interconnects a serial communications bus of the system processor and the peripheral controller interface. The incompatible systems interface includes a processor programmed to receive, decode and transmit information from or to the system processor along the serial bus and load or receive information from or to the peripheral controller interface along parallel lines. The communication timing constraints of the serial communications bus for receipt of data signals by the system processor do not permit monitoring of the data transmission by the incompatible systems processor.

Abstract: A peripheral interface board establishes a communications link between a postage value determining system processor associated with a postage scale and a plurality of peripheral devices. The interface includes a microcomputer which receives data and command signals from the system processor. A multiplexer interconnects the peripheral transmit line of the microcomputer with a selected peripheral device, while a further multiplexer interconnects the peripheral receive line of the microcomputer with the selected peripheral device. Typical mailing system peripheral devices include electronic postage meters, an electronic accounting system, a scale computer interface and a printer. In response to command signals from the system processor, the microcomputer establishes a communications link with a selected peripheral device.

Abstract: A processor controlled automated mailing system for determining and printing the requisite postage for mailing an article includes a scale, a keyboard for operator input, a display and a meter setting device. After the requisite postage has been determined, a postage printing cycle is initiated by the operator. The processor determines whether the calculated postage value exceeds the digit printing capacity of the meter and, if so, advises the operator. The operator then determines if an entry error has been made and if not, reactivates the printing cycle. The processor thereafter initiates the meter setting device to sequentially print multiple tapes with each depression of the print key until the total value printed reaches the calculated postage value. An alternate embodiment incorporates a circuit for implementation of the method without processor control.

Abstract: A postage value calculator system includes a processor which receives article weight, destination, class and carrier type information for transportation of the article. The processor accesses a directory which vectors to memory locations to retrieve rate data for generation of a postage value. The system includes an address counter which is incremented to access successive memory address locations. All system memories include uniformly spaced storage locations which are reserved for addressing purposes only. Each time the address counter is incremented, a check is made to determine if the location reached is reserved for addressing data. If the location is not reserved for addressing data, the stored postal information is used for the postage computation routine. When the incremented address is that of the addressing data, the word stored in the memory is loaded into the upper byte of the address counter, the lower order byte is set to zero, and the program continues at the new address.

Abstract: A multiprocessor parcel postage metering system includes a system processor to which a scale subsystem processor, a postage printing subsystem processor and a peripherals subsystem processor may be connected. The processors share a common data bus over which data is transferred serially. The system processor accepts weight and status data transmitted from the scale subsystem processor over the serial data bus. The system processor operates on this data and keyboard entry data to calculate required postage as a function of parcel origin, parcel destination, class of service and selected special fees. Printer setting data is transferred to the postage printing subsystem processor over the serial data bus. Peripheral devices, such as a document printer or a parcel identification number counter, are controlled by data sent to the peripherals subsystem processor over the serial data bus.

Abstract: A system for mailing articles includes an integrated circuit interface between a scale deflection transducer, a processor and an external memory. The interface includes a multifunction shift register array which is adapted to receive count data indicative of the weight of an article. Communication between the shift register array, the processor and the memory is such that the shift registers are selectively utilized for memory address and data transfer without the necessity of clearing prior operands.

Abstract: A postage value computing system includes both apparatus and a method for determining the postage of an article to be mailed for various domestic and international classes of postal service. Postal information such as carrier type, class and destination data are introduced into the system and used to access a memory which stores common structured rate data. Major rate structures are defined by weight headers which specify the upper and lower limits of weight ranges and the weight increments within those ranges. To minimize memory requirements, foreign countries are grouped as a function of such common structured rate data including permissible weight limits. Memory space is conserved through the utilization of a common postage computation routine including various equation subroutines for generating requisite postage values in accordance with the retrieved postage rate data.

Abstract: A multiprocessor parcel postage metering system includes a system processor to which a scale subsystem processor, a postage printing subsystem processor, and a peripherals subsystem processor may be connected. The processors share a common data bus over which data is transferred serially. The system processor accepts weight and status data transmitted from the scale subsystem processor over the serial data bus. The system processor operates on this data and keyboard entry data to calculate required postage as a function of parcel origin, parcel destination, class of service and selected special fees. Printer setting data is transferred to the postage printing subsystem processor over the serial data bus. Peripheral devices, such as a document printer or a parcel identification number counter, are controlled by data sent to the peripherals subsystem processor over the serial data bus. Each transmission is verified by returning the complemented form of a transmitted word to the sending processor.

Abstract: A system for mailing articles includes an integrated circuit interface between a scale deflection transducer, a processor and an external memory. The interface includes a multifunction shift register array which is adapted to receive count data indicative of the weight of an article. Communication between the shift register array, the processor and the memory is such that the shift registers are selectively utilized for memory address and data transfer without the necessity of clearing prior operands.

Abstract: A system for processing cyclic signal pairs generated by an optical transducer to provide an accurate measurement of the displacement of one member with respect to a reference is suitable for determining weight by measuring spring scale tare deflection. The system includes a pair of comparator Schmitt trigger circuits for shaping pulse waveform signals. The pulse signals are processed by fully clocked digital circuits including edge discriminators to generate multiple count pulses which are processed by combination logic for direction determination. Further processing includes sign determination (positive-negative) and zero identification circuits to provide up and down pulses which are filtered and fed to up/down counter stages. Counter stage information is decoded for feedback control and processing logic indication.

Abstract: For averaging a selected number of input values, a circuit includes a counter which is enabled to count up to the selected number. During the counting, samples of input values are synchronously loaded into an accumulator circuit having shift capabilities. A control circuit responds to a selected number in the counter to load a binary 1 into a related stage in a shift register. The control circuit causes the binary 1 to be shifted through the register while the contents of the accumulator circuit are synchronously shifted toward the least significant bit of the accumulator circuit to effect a binary division. Both shift operations are terminated by a shift stop circuit which detects the presence of the binary 1 signal at a predetermined shift register stage.

Abstract: In a data processing system wherein operator entry of data is provided an array of alpha numeric display units is utilized not only for indicating operand entries and operating results, but also as an operator message prompting medium for steering the operator to correct operand entry or system errors. Upon processor recognition of a particular entry or other errors an assigned error signal is generated which blocks the operand or operation result signal from the display units. In one embodiment the error signal is received at a programable logic array associated with each display unit to provide a signal for accessing a memory which in turn provides the appropriate letter pattern signal for the display unit to spell out an error prompt message. An alternate embodiment provides for serial generation of the letter pattern signals for each display unit and rapid sequential actuation of the display units to spell the prompt message.