Abstract: A method and circuit for processing a serial data stream carrying data at a rate established by an underlying clock signal, the method and circuit involving: time-stamping each of the transitions of a sequence of transitions within the serial data stream to thereby generate a sequence of time stamps; and based at least in part on the sequence of time-stamps, recovering the data from the serial data stream.

Abstract: A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a cock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms. In one form, this data is determined a priori from simulations or experiments made on a particular VRM or power supply unit and used to generate and store parameters that are known to optimally (quickly and without degradation of VRM or power supply performance) change the frequency of the clock processing circuit.

Abstract: A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal.

Abstract: A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal.

Abstract: A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented. A selector circuit is responsive to the delay control signal and converts the delay control signal into one or more transistor selection signals to activate one or more of the plurality of transistors. The plurality of transistors may comprise a first sub-circuit having a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other in a ladder configuration, and a second sub-circuit comprising a plurality of transistors of a second type (e.g.

Abstract: A clock signal generation system and method to distribute at least one clock signal to a plurality of points on a circuit board using a plurality of digitally programmable delay circuits each of which delays the clock signal by a desired amount so as to synchronize arrival of the clock signal when distributed to each of the plurality of points on the circuit. Each digitally programmable delay circuit comprises a plurality of circuit stages connected in series with each other. Each circuit stage comprises a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other, and a plurality of transistors of a second type (e.g., N-type) connected in parallel with each other. In each circuit stage, one or more of the plurality of transistors of the first type are selected to delay a rising edge, and one or more of the plurality of transistors of a second type are selected to delay a falling edge.

Abstract: An ice fishing trap comprising a main body supporting a rotatable spool for supporting a desired length of fishing line. An indicator, having both a set position and a triggered position, is supported by the main body. A release rod cooperates with the rotatable spool and, when the indicator is in its set position, and also cooperates with the indicator. The release rod has a first position in which the release rod captively retains the indicator in its set position and engages with the spool and the release rod has a second position, axially spaced from the first position, in which the release rod releases the indicator to permit the indicator to move to its triggered position, and rotation of the spool moves the release rod from its first position to its second position to actuate the indicator into its triggered position.

Abstract: The methods described herein are directed at securing information in storage media such as optical discs, magnetic disks or a combination thereof. In particular the methods describe embedding a first stream of data in a second stream of data by modulating the location of transition edges in the second stream of data. A method for writing data to a storage medium includes the steps of representing the raw (first) data to be written to the storage medium as a sequence of bits in a format appropriate for writing to a storage medium; representing second data (supplemental data) as a second sequence of bits and writing the first sequence of bits to the storage medium as a corresponding sequence of pits along a track, wherein the location of the pits along the track represents the stored first data, and while writing the first sequence of pits, modulating the locations at which transition edges of the sequence of pits are written to embed the second data in the sequence of pits.

Abstract: A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented. A selector circuit is responsive to the delay control signal and converts the delay control signal into one or more transistor selection signals to activate one or more of the plurality of transistors. The plurality of transistors may comprise a first sub-circuit having a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other in a ladder configuration, and a second sub-circuit comprising a plurality of transistors of a second type (e.g.

Abstract: A waveform generator includes a plurality of delay elements such as in a delay line circuit of a free-running oscillator, phase locked loop (PLL) circuit or delay locked loop (DLL) circuit, an algebra module, a switching module and an output module. The oscillator includes a plurality of delay elements and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module includes an algebra data input port, a clock input port and an algebra data output port. The algebra module generates a signal at the algebra data output port indicating a first rising edge of the arbitrary waveform in response to a signal received at the algebra data input port. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication oscillator taps and switch output port.

Abstract: A method of processing a serial data stream carrying data at a rate established by an underlying clock signal, the method involving: time-stamping each of the transitions of a sequence of transitions within the serial data stream to thereby generate a sequence of time-stamps; and based at least in part on the sequence of time-stamps, recovering the data from the serial data stream.

Abstract: The present invention relates to a method of adaptively enhancing a digital image based on image content. An accurate determination of image type permits implementation of an image enhancement technique that is matched to the image type. The method is advantageous when the image type of the received images can vary. In one embodiment the method distinguishes between line art images and continuous tone images. The method includes application of a window to a pixels in a source array. The number of colors in each of the resulting windowed arrays is determined. Each color can optionally be defined as a range of colors. A color range total is calculated from the sum of the number of windowed arrays in one or more subsets of the plurality of possible numbers of colors. Image type is determined in response to the color range total and an enhancement process matched to the image type is applied to the digital image data.

Abstract: A method for enhancing a digital image for printing or display on a high resolution device is described. The method includes receiving a digital source image and selecting a block of source pixels from the image. An edge array is generated from edges detected in the block of source pixels and processed with a set of logic operations to detect one of a set of edge patterns. The source coordinate system is transformed into a second coordinate system in response to the detected edge pattern and a transformed source location for the output pixel is determined. A modified transformed source location is determined by applying a modifier function. The modifier function is selected from a set of functions in response to the detected edge pattern. An effective source location is generated by applying a reverse transformation. The value of the output pixel is interpolated from the values of the block of source pixels based on the effective source location.

Abstract: A method of recovering a pixel clock for generating a digital image from an analog video signal is presented. The on and off-transition times for the active video portion of a digital image and the image size defined in a video standard are used to generate a pixel clock. The analog video signal is digitized according to the pixel clock and the image size of the resulting digital image is compared with the image size defined in the video standard. The pixel clock frequency is adjusted in response to the image size comparison. The optimum phase of the pixel clock relative to the analog video signal is determined through a repetitive phase adjustment technique. A first image coordinate is determined for a pixel clock at one phase and a subsequent image coordinate is determined for a pixel clock after decrementing the phase of the pixel clock. The first image coordinate and the subsequent image are compared.

Abstract: A method and apparatus for the scaling of digital image data for improved image quality on LCD displays is described. An output pixel value is determined from a source pixel array approximately centered at the output pixel location. Edge arrays are generated by comparing the differences in the color component values of adjacent vertical and horizontal pixels to a threshold value. Logic arrays operate on edge arrays to determine if the source pixel array matches predetermined pixel arrangements. Offset values corresponding to the location of the output pixel relative to the center pixel in the source pixel array are calculated. The offset values are modified if a logic array match is found. Offset values are also modified according to a predetermined modifier function. Bilinear interpolation based on the resulting offset values is used to determine the output pixel value.

Abstract: A grayscale enhancement system which operates on color or monochrome source halftone images to produce output halftone cells of the same visual weight but spatially distributed to reduce artifacts caused by limited grayscale levels. By operating upon a set of input halftone cells surrounding each output pixel cell with a set of logic operations implementing unique algorithms, the system re-distributes the weight of the halftone cells characterizing inferred-halftone cells. A rendering subsystem, responsive to the inferred-halftones, then produces signal for driving an output device to the best of the output device's ability.