Patents by Inventor Daniel J. Blomberg

Daniel J. Blomberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10217860
    Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: February 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Hongning Yang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 10186612
    Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: January 22, 2019
    Assignee: NXP USA, Inc.
    Inventors: Hongning Yang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 9917150
    Abstract: Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 13, 2018
    Assignee: NXP USA, INC.
    Inventors: Xu Cheng, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 9893164
    Abstract: A method of fabricating a bipolar transistor device includes performing a first plurality of implantation procedures to implant dopant of a first conductivity type to form emitter and collector regions laterally spaced from one another in a semiconductor substrate, and performing a second plurality of implantation procedures to implant dopant of a second conductivity type in the semiconductor substrate to form a composite base region. The composite base region includes a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: February 13, 2018
    Assignee: NXP USA, INC.
    Inventors: Xin Lin, Daniel J Blomberg, Jiang-Kai Zuo
  • Patent number: 9728600
    Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area, and a body region disposed in the semiconductor substrate within the core device area, and in which a channel is formed during operation. The body region is electrically tied to the isolation contact region. The body region and the doped isolation barrier have a common conductivity type. The body region is electrically isolated from the doped isolation barrier within the core device area. The doped isolation barrier and the isolation contact region are not electrically tied to one another such that the doped isolation barrier is biased at a different voltage level than the isolation contact region.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: August 8, 2017
    Assignee: NXP USA, Inc.
    Inventors: Hongning Yang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 9680011
    Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate, and having a conductivity type in common with the doped isolation barrier and the drain region. The depleted well region is positioned between the doped isolation barrier and the drain region to electrically couple the doped isolation barrier and the drain region such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the drain region.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: June 13, 2017
    Assignee: NXP USA, Inc.
    Inventors: Zhihong Zhang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 9647082
    Abstract: A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type; and a second contact region disposed at the surface, laterally spaced from the first contact region, and having a second conductivity type. The diode also includes a buried region disposed in the semiconductor substrate vertically adjacent to the first contact region, having the second conductivity type, and electrically connected with the second contact region; and an isolation region disposed at the surface between the first and second contact regions. The diode also includes a separation region disposed at the surface between the first contact region and the isolation region, the separation region formed from a portion of a first well region disposed in the semiconductor substrate that extends to the surface.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: May 9, 2017
    Assignee: NXP USA, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
  • Publication number: 20170125584
    Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate, and having a conductivity type in common with the doped isolation barrier and the drain region. The depleted well region is positioned between the doped isolation barrier and the drain region to electrically couple the doped isolation barrier and the drain region such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the drain region.
    Type: Application
    Filed: October 29, 2015
    Publication date: May 4, 2017
    Inventors: Zhihong Zhang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 9640635
    Abstract: A method of fabricating a transistor device having a channel of a first conductivity type formed during operation in a body region having a second conductivity type includes forming a first well region of the body region in a semiconductor substrate, performing a first implantation procedure to counter-dope the first well region with dopant of the first conductivity type to define a second well region of the body region, and performing a second implantation procedure to form a source region in the first well region and a drain region in the second well region.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: May 2, 2017
    Assignee: NXP USA, INC.
    Inventors: Zhihong Zhang, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
  • Publication number: 20170110537
    Abstract: Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.
    Type: Application
    Filed: December 30, 2016
    Publication date: April 20, 2017
    Inventors: Xu Cheng, Daniel J. Blomberg, Jiang-Kai Zuo
  • Publication number: 20170084715
    Abstract: A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type; and a second contact region disposed at the surface, laterally spaced from the first contact region, and having a second conductivity type. The diode also includes a buried region disposed in the semiconductor substrate vertically adjacent to the first contact region, having the second conductivity type, and electrically connected with the second contact region; and an isolation region disposed at the surface between the first and second contact regions. The diode also includes a separation region disposed at the surface between the first contact region and the isolation region, the separation region formed from a portion of a first well region disposed in the semiconductor substrate that extends to the surface.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: XIN LIN, DANIEL J. BLOMBERG, HONGNING YANG, JIANG-KAI ZUO
  • Patent number: 9601595
    Abstract: A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 21, 2017
    Assignee: NXP USA, INC.
    Inventors: Hongning Yang, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 9601564
    Abstract: An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: March 21, 2017
    Assignee: NXP USA, INC.
    Inventors: Xu Cheng, Daniel J. Blomberg, Zhihong Zhang, Jiang-Kai Zuo
  • Publication number: 20170077219
    Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area, and a body region disposed in the semiconductor substrate within the core device area, and in which a channel is formed during operation. The body region is electrically tied to the isolation contact region. The body region and the doped isolation barrier have a common conductivity type. The body region is electrically isolated from the doped isolation barrier within the core device area. The doped isolation barrier and the isolation contact region are not electrically tied to one another such that the doped isolation barrier is biased at a different voltage level than the isolation contact region.
    Type: Application
    Filed: September 11, 2015
    Publication date: March 16, 2017
    Inventors: Hongning Yang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Zhihong Zhang, Jiang-Kai Zuo
  • Publication number: 20170077295
    Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region.
    Type: Application
    Filed: September 11, 2015
    Publication date: March 16, 2017
    Inventors: Hongning Yang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 9590097
    Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body region of semiconductor material having a first conductivity type, a source region of semiconductor material having a second conductivity type within the body region, a junction isolation region of semiconductor material having the second conductivity type, a drain region of semiconductor material having the second conductivity type, and first and second drift regions of semiconductor material having the second conductivity type. The first drift region resides laterally between the drain region and the junction isolation region, the junction isolation region resides laterally between the first drift region and the second drift region, and the second drift region resides laterally between the body region and the junction isolation region.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: March 7, 2017
    Assignee: NXP USA, INC.
    Inventors: Hongning Yang, Daniel J. Blomberg, Xin Lin, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 9570548
    Abstract: Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: February 14, 2017
    Assignee: NXP USA, INC.
    Inventors: Xu Cheng, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 9543454
    Abstract: A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type; and a second contact region disposed at the surface, laterally spaced from the first contact region, and having a second conductivity type. The diode also includes a buried region disposed in the semiconductor substrate vertically adjacent to the first contact region, having the second conductivity type, and electrically connected with the second contact region; and an isolation region disposed at the surface between the first and second contact regions. The diode also includes a separation region disposed at the surface between the first contact region and the isolation region, the separation region formed from a portion of a first well region disposed in the semiconductor substrate that extends to the surface.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 10, 2017
    Assignee: NXP USA, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 9496333
    Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a RESURF anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: November 15, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 9466687
    Abstract: Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: October 11, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xin Lin, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo