Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.

Abstract: Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration CFE, and a second emitter (SE) portion (42-2) of a second dopant concentration CSE. Preferably CSE?CFE. The SE portion (42-2) desirably comprises multiple sub-regions (45i, 45j, 45k) mixed with multiple sub-regions (47m, 47n, 47p) of the FE portion (42-1). A semiconductor-metal alloy or compound (e.g., a silicide) is desirably used for Ohmic contact (452) to the SE portion (42-2) but substantially not to the FE portion (42-1). Including the FE portion (42-1) electrically coupled to the SE portion (42-2) but not substantially contacting the emitter contact (452) on the SE portion (42-2) provides gain increases of as much as ˜278.

Abstract: Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration CFE, and a second emitter (SE) portion (42-2) of a second dopant concentration CSE. Preferably CSE?CFE. The SE portion (42-2) desirably comprises multiple sub-regions (45i, 45j, 45k) mixed with multiple sub-regions (47m, 47n, 47p) of the FE portion (42-1). A semiconductor-metal alloy or compound (e.g., a silicide) is desirably used for Ohmic contact (452) to the SE portion (42-2) but substantially not to the FE portion (42-1). Including the FE portion (42-1) electrically coupled to the SE portion (42-2) but not substantially contacting the emitter contact (452) on the SE portion (42-2) provides gain increases of as much as ˜278.

Abstract: Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration CFE, and a second emitter (SE) portion (42-2) of a second dopant concentration CSE. Preferably CSE?CFE. The SE portion (42-2) desirably comprises multiple sub-regions (45i, 45j, 45k) mixed with multiple sub-regions (47m, 47n, 47p) of the FE portion (42-1). A semiconductor-metal alloy or compound (e.g., a silicide) is desirably used for Ohmic contact (452) to the SE portion (42-2) but substantially not to the FE portion (42-1). Including the FE portion (42-1) electrically coupled to the SE portion (42-2) but not substantially contacting the emitter contact (452) on the SE portion (42-2) provides gain increases of as much as ˜278.

Abstract: Embodiments for forming improved bipolar transistors are provided, manufacturable by a CMOS IC process. The improved transistor comprises an emitter having first and second portions of different depths, a base underlying the emitter having a central portion of a first base width underlying the first portion of the emitter, a peripheral portion having a second base width larger than the first base width partly underlying the second portion of the emitter, and a transition zone of a third base width and lateral extent lying laterally between the first and second portions of the base, and a collector underlying the base. The gain of the transistor is larger than a conventional bipolar transistor made using the same CMOS process. By adjusting the lateral extent of the transition zone, the properties of the improved transistor can be tailored to suit different applications without modifying the underlying CMOS IC process.

Abstract: Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration CFE, and a second emitter (SE) portion (42-2) of a second dopant concentration CSE. Preferably CSE?CFE. The SE portion (42-2) desirably comprises multiple sub-regions (45i, 45j, 45k) mixed with multiple sub-regions (47m, 47n, 47p) of the FE portion (42-1). A semiconductor-metal alloy or compound (e.g., a silicide) is desirably used for Ohmic contact (452) to the SE portion (42-2) but substantially not to the FE portion (42-1). Including the FE portion (42-1) electrically coupled to the SE portion (42-2) but not substantially contacting the emitter contact (452) on the SE portion (42-2) provides gain increases of as much as ˜278.

Abstract: An improved bipolar transistor (40, 40?) is provided, manufacturable by a CMOS IC process without added steps. The improved transistor (40, 40?) comprises an emitter (48) having first (482) and second (484) portions of different depths (4821, 4841), a base (46) underlying the emitter (48) having a central portion (462) of a first base width (4623) underlying the first portion (482) of the emitter (48), a peripheral portion (464) having a second base width (4643) larger than the first base width (4623) partly underlying the second portion (484) of the emitter (48), and a transition zone (466) of a third base width (4644) and lateral extent (4661) lying laterally between the first (462) and second (464) portions of the base (46), and a collector (44) underlying the base (46). The gain of the transistor (40, 40?) is much larger than a conventional bipolar transistor (20) made using the same CMOS process.

Abstract: A Zener diode is fabricated on a semiconductor substrate having semiconductor material thereon. The Zener diode includes a first well region having a first conductivity type, formed in the semiconductor material. The Zener diode also includes a first region having a second conductivity type, formed in the first well region (the second conductivity type is opposite the first conductivity type). The Zener diode also includes a second region having the first conductivity type, wherein the second region is formed in the first well region and overlying the first region. An electrode is formed in the first region, and the electrode is electrically coupled to the second region.

Abstract: Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface.

Abstract: Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact, the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.

Abstract: Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact, the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.

Abstract: A Zener diode is fabricated on a semiconductor substrate having semiconductor material thereon. The Zener diode includes a first well region having a first conductivity type, formed in the semiconductor material. The Zener diode also includes a first region having a second conductivity type, formed in the first well region (the second conductivity type is opposite the first conductivity type). The Zener diode also includes a second region having the first conductivity type, wherein the second region is formed in the first well region and overlying the first region. An electrode is formed in the first region, and the electrode is electrically coupled to the second region.

Abstract: Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.

Abstract: An improved bipolar transistor (40, 40?) is provided, manufacturable by a CMOS IC process without added steps. The improved transistor (40, 40?) comprises an emitter (48) having first (482) and second (484) portions of different depths (4821, 4841), a base (46) underlying the emitter (48) having a central portion (462) of a first base width (4623) underlying the first portion (482) of the emitter (48), a peripheral portion (464) having a second base width (4643) larger than the first base width (4623) partly underlying the second portion (484) of the emitter (48), and a transition zone (466) of a third base width (4644) and lateral extent (4661) lying laterally between the first (462) and second (464) portions of the base (46), and a collector (44) underlying the base (46). The gain of the transistor (40, 40?) is much larger than a conventional bipolar transistor (20) made using the same CMOS process.

Abstract: Improved Schottky diodes (20) with reduced leakage current and improved breakdown voltage are provided by building a JFET (56) into the diode, serially located in the anode-cathode current path (32). The gates of the JFET (56) formed by doped regions (38, 40) placed above and below the diode's current path (32) are coupled to the anode (312) of the diode (20), and the current path (32) passes through the channel region (46) of the JFET (56). Operation is automatic so that as the reverse voltage increases, the JFET (56) channel region (46) pinches off, thereby limiting the leakage current and clamping the voltage across the Schottky junction (50) at a level below the Schottky junction (50) breakdown. Increased reverse voltage can be safely applied until the device eventually breaks down elsewhere. The impact on device area and area efficiency is minimal and the device can be built using a standard fabrication process so that it can be easily integrated into complex ICs.

Abstract: An improved device (20) is provided, comprising, merged vertical (251) and lateral transistors (252), comprising thin collector regions (34) of a first conductivity type sandwiched between upper (362) and lower (30) base regions of opposite conductivity type that are Ohmically coupled via intermediate regions (32, 361) of the same conductivity type and to the base contact (38). The emitter (40) is provided in the upper base region (362) and the collector contact (42) is provided in outlying sinker regions (28) extending to the thin collector regions (34) and an underlying buried layer (28). As the collector voltage increases part of the thin collector regions (34) become depleted of carriers from the top by the upper (362) and from the bottom by the lower (30) base regions. This clamps the thin collector regions' (34) voltage well below the breakdown voltage of the PN junction formed between the buried layer (28) and the lower base region (30).

Abstract: Improved Schottky diodes (20, 20?) with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path (50, 50?) of a first conductivity type serially located between a first terminal (80, 80?, 32, 32?) comprising a Schottky contact (33, 33?) and a second (82, 82?, 212, 212?) terminal. The current path (50, 50?) lies (i) between multiple substantially parallel finger regions (36, 36?) of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact (33, 33?), and (ii) partly above a buried region (44, 44?) of the second conductivity type that underlies a portion (46, 46?) of the current path (50, 50?), which regions (36, 36?; 44, 44?) are electrically coupled to the first terminal (80, 80?, 32, 32?) and the Schottky contact (33, 33?) and which portion (46, 46?) is electrically coupled to the second terminal (82, 82?, 212, 212?).

Abstract: Improved Schottky diodes (20) with reduced leakage current and improved breakdown voltage are provided by building a JFET (56) into the diode, serially located in the anode-cathode current path (32). The gates of the JFET (56) formed by doped regions (38, 40) placed above and below the diode's current path (32) are coupled to the anode (312) of the diode (20), and the current path (32) passes through the channel region (46) of the JFET (56). Operation is automatic so that as the reverse voltage increases, the JFET (56) channel region (46) pinches off, thereby limiting the leakage current and clamping the voltage across the Schottky junction (50) at a level below the Schottky junction (50) breakdown. Increased reverse voltage can be safely applied until the device eventually breaks down elsewhere. The impact on device area and area efficiency is minimal and the device can be built using a standard fabrication process so that it can be easily integrated into complex ICs.