Patents by Inventor Daniel J. Friedman

Daniel J. Friedman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200350234
    Abstract: An exemplary assembly includes a top circuit substrate; a bottom circuit assembly that underlays the top circuit substrate and is attached to the top circuit substrate by an adhesive layer as a stiffener, the adhesive layer, and a plurality of conductive balls. The top circuit substrate includes a plurality of upper vias that extend through the top circuit substrate. The bottom circuit assembly includes a plurality of lower vias that extend through the bottom circuit assembly. The adhesive layer includes internal connections that electrically connect the upper vias to the lower vias. The conductive balls are housed in the lower vias. The bottom circuit assembly has an elastic modulus at least six times the elastic modulus of the top circuit substrate, and has a coefficient of thermal expansion at least two times the coefficient of thermal expansion of the top circuit substrate.
    Type: Application
    Filed: May 3, 2019
    Publication date: November 5, 2020
    Inventors: LEI SHAN, DANIEL J. FRIEDMAN
  • Patent number: 10810487
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20200269032
    Abstract: A system including a plurality of indicator tags, each of which includes a body having a first end, a second end, a first surface extending from the first end to the second end, a second surface extending from the first end to the second end, and an aperture sized and shaped to receive a corresponding intravenous tube extending from the first end to the second end intermediate the first surface and the second surface, at least one of the first and second surfaces including a haptic signature, wherein the plurality of indicator tags includes at least one tag of a first type and at least one tag of a second type, wherein the haptic signature of the at least one tag of the first type corresponds to a first medication, wherein the haptic signature of the at least one tag of the second type corresponds to a second medication.
    Type: Application
    Filed: March 3, 2020
    Publication date: August 27, 2020
    Applicant: Star Luminal LLC
    Inventors: David J. Friedman, Elizabeth S. Friedman, Daniel O. Hogenauer, Eric A. Haddad, Bryce G. Rutter, Max W. Ryan, Tucker P. Brown
  • Publication number: 20200161744
    Abstract: Antenna package structures are provided to implement wireless communications packages. For example, an antenna package includes multilayer package substrate, a planar antenna array, antenna feed lines, and resistive transmission lines. The planar antenna array includes an array of active antenna elements and dummy antenna elements surrounding the array of active antenna elements. Each active antenna element is coupled to a corresponding one of the antenna feed lines, and each dummy antenna element is coupled to a corresponding one of the resistive transmission lines. Each resistive transmission line extends through the multilayer package substrate and is terminated in a same metallization layer of the multilayer package substrate.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Christian W. Baks, Daniel J. Friedman, Xiaoxiong Gu, Duixian Liu, Alberto Valdes Garcia, Joakim Hallin, Ola Ragnar Tageman
  • Patent number: 10628732
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Patent number: 10594019
    Abstract: Antenna package structures are provided to implement wireless communications packages. For example, an antenna package includes multilayer package substrate, a planar antenna array, antenna feed lines, and resistive transmission lines. The planar antenna array includes an array of active antenna elements and dummy antenna elements surrounding the array of active antenna elements. Each active antenna element is coupled to a corresponding one of the antenna feed lines, and each dummy antenna element is coupled to a corresponding one of the resistive transmission lines. Each resistive transmission line extends through the multilayer package substrate and is terminated in a same metallization layer of the multilayer package substrate.
    Type: Grant
    Filed: December 3, 2016
    Date of Patent: March 17, 2020
    Assignees: International Business Machines Corporation, Ericsson AB
    Inventors: Christian W. Baks, Daniel J. Friedman, Xiaoxiong Gu, Duixian Liu, Alberto Valdes Garcia, Joakim Hallin, Ola Ragnar Tageman
  • Publication number: 20200069866
    Abstract: An indicator includes a body having a first end, a second end opposite the first end, a first surface and a second surface opposite the first surface, each of which extends from the first end to the second end, and an aperture extending from the first end to the second end, the aperture being sized and shaped to receive a tube, and at least one of the first and second surfaces including a haptic signature formed thereon.
    Type: Application
    Filed: August 1, 2019
    Publication date: March 5, 2020
    Applicant: Star Luminal LLC
    Inventors: David J. Friedman, Elizabeth S. Friedman, Daniel O. Hogenauer, Eric A. Haddad, Bryce G. Rutter, Max W. Ryan, Tucker P. Brown
  • Patent number: 10579092
    Abstract: Aspects include a method for generating a signal in response to an event. The method includes receiving, from a clock signal generator, a clock signal, wherein the clock signal has a fixed clock period. The method further includes receiving an indication of a pulse and, responsive to receiving the indication of the pulse, generating an output comprising a high voltage having a starting time and an ending time. The starting time is a first time when the indication of the asynchronous event is received, and the ending time is a second time at one fixed clocked period from the starting time.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel J. Friedman, Seongwon Kim, Bipin Rajendran
  • Publication number: 20200019731
    Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
    Type: Application
    Filed: September 21, 2019
    Publication date: January 16, 2020
    Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
  • Publication number: 20200019732
    Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
    Type: Application
    Filed: September 21, 2019
    Publication date: January 16, 2020
    Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
  • Publication number: 20200012962
    Abstract: A technology is described for automating deployment of a machine learning model. An example method may include receiving, via a graphical user interface, credentials for connecting to a data store containing a plurality of datasets and connecting to the data store using the credentials. A selection of a target metric to predict using the machine learning model can be received, via the graphical user interface, and datasets included in the plurality of datasets that correlate to the target metric can be identified by analyzing the datasets to identify an association between the target metric and data contained within the datasets. The datasets can be input to the machine learning model to train the machine learning model to generate predictions of the target metric, and the machine learning model can be deployed to computing resources in a service provider environment to generate predictions associated with the target metric.
    Type: Application
    Filed: May 20, 2019
    Publication date: January 9, 2020
    Inventors: Killian B. Dent, James M. Friedman, Allan D. Johnson, Shauna J. Moran, Tyler P. Cooper, Chris K. Knoch, Nicholas R. Magnuson, Daniel J. Wallace
  • Publication number: 20190356375
    Abstract: A method and system of a configurable phased array transceiver are provided. A first beamforming unit is configured to provide a first beam. A second beamforming unit is configured to provide a second beam. A first bi-directional power controller is configured to combine or to split the first beam and the second beam. Each beamforming unit comprises a plurality of radio frequency (RF) front-ends, each front-end being configured to transmit and receive RF signals. Each beam is independently configurable to operate in a transmit (TX) or a receive (RX) mode.
    Type: Application
    Filed: August 2, 2019
    Publication date: November 21, 2019
    Inventors: Daniel J. Friedman, Joakim Hallin, Yahya Mesgarpour Tousi, Orjan Renstrom, Leonard Rexberg, Scott K. Reynolds, Bodhisatwa Sadhu, Stefan Sahl, Jan-Erik Thillberg, Alberto Valdes Garcia
  • Patent number: 10423805
    Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
  • Patent number: 10425143
    Abstract: A method and system of a configurable phased array transceiver are provided. A first beamforming unit is configured to provide a first beam. A second beamforming unit is configured to provide a second beam. A first bi-directional power controller is configured to combine or to split the first beam and the second beam. Each beamforming unit comprises a plurality of radio frequency (RF) front-ends, each front-end being configured to transmit and receive RF signals. Each beam is independently configurable to operate in a transmit (TX) or a receive (RX) mode.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel J. Friedman, Joakim Hallin, Yahya Mesgarpour Tousi, Örjan Renström, Leonard Rexberg, Scott K. Reynolds, Bodhisatwa Sadhu, Stefan Sahl, Jan-Erik Thillberg, Alberto Valdes Garcia
  • Patent number: 10367513
    Abstract: A phase-locked loop circuit includes an oscillator, a frequency control device, the frequency control device generating a frequency control signal that controls a frequency of the oscillator, and a bias optimizer that monitors the frequency control device and generates a bias voltage for the oscillator, the oscillator includes a transfer function from bias voltage to frequency that is proportional to a transfer function from a low frequency noise component to frequency, the transfer function from bias voltage to frequency having a convex shape with a local minimum at which a sensitivity of the frequency to changes in the bias voltage is zero, and the bias voltage from the bias optimizer is set to the local minimum.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Ferriss, Daniel J. Friedman, Bodhisatwa Sadhu, Wooram Lee
  • Publication number: 20190228289
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Patent number: 10331998
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20190165796
    Abstract: A phase-locked loop circuit includes an oscillator, a frequency control device, the frequency control device generating a frequency control signal that controls a frequency of the oscillator, and a bias optimizer that monitors the frequency control device and generates a bias voltage for the oscillator, the oscillator includes a transfer function from bias voltage to frequency that is proportional to a transfer function from a low frequency noise component to frequency, the transfer function from bias voltage to frequency having a convex shape with a local minimum at which a sensitivity of the frequency to changes in the bias voltage is zero, and the bias voltage from the bias optimizer is set to the local minimum.
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventors: Mark A. Ferriss, Daniel J. Friedman, Bodhisatwa Sadhu, Wooram Lee
  • Patent number: 10255467
    Abstract: RFID (radio frequency identification) systems are provided in which tag and interrogator devices implement a hybrid framework for signaling including an optical transmitter/receiver system and an RF transmitter/receiver system. For instance, an RFID tag device includes: optical receiver circuitry configured to receive an optical signal having an embedded clock signal from an interrogator device, and convert the optical signal into an electrical signal comprising the embedded clock signal; clock extraction circuitry configured to extract the embedded clock signal from the electrical signal, and output the extracted clock signal as a clock signal for controlling clocking functions of the tag device; voltage regulator circuitry configured to generate a regulated supply voltage from the electrical signal, wherein the regulated supply voltage is utilized as a bias voltage for components of the tag device; and data transmitter circuitry configured to wirelessly transmit tag data to the interrogator device.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Friedman, Duixian Liu, Mihai A. Sanduleanu
  • Patent number: 10211779
    Abstract: A voltage controlled oscillator comprises a negative resistance, a first inductor, a fixed capacitor, and a frequency control component. The frequency control component comprises at least one varactor and at least a second inductor connected in series with the at least one varactor. A magnitude of an inductance of the second inductor is selected such that the frequency control component has an effective capacitance range larger than a capacitance range of the at least one varactor.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Ferriss, Daniel J. Friedman, Bodhisatwa Sadhu, Alberto Valdes-Garcia