Patents by Inventor Daniel J. Friedman

Daniel J. Friedman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180069309
    Abstract: A method and system of a configurable phased array transceiver are provided. A first beamforming unit is configured to provide a first beam. A second beamforming unit is configured to provide a second beam. A first bi-directional power controller is configured to combine or to split the first beam and the second beam. Each beamforming unit comprises a plurality of radio frequency (RF) front-ends, each front-end being configured to transmit and receive RF signals. Each beam is independently configurable to operate in a transmit (TX) or a receive (RX) mode.
    Type: Application
    Filed: May 16, 2017
    Publication date: March 8, 2018
    Inventors: Daniel J. Friedman, Joakim Hallin, Yahya Mesgarpour Tousi, Örjan Renström, Leonard Rexberg, Scott K. Reynolds, Bodhisatwa Sadhu, Stefan Sahl, Jan-Erik Thillberg, Alberto Valdes Garcia
  • Patent number: 9837959
    Abstract: An apparatus comprises a digitally controlled circuit having a variable capacitance and a controller configured to adjust a magnitude of the variable capacitance of the digitally controlled circuit. The digitally controlled circuit comprises a plurality of gain elements, the plurality of gain elements comprising one or more positive voltage-to-frequency gain elements and one or more negative voltage-to-frequency gain elements. The controller is configured to adjust the magnitude of the capacitance by adjusting the gain provided by respective ones of the gain elements in an alternating sequence of the positive voltage-to-frequency gain elements and the negative voltage-to-frequency gain elements.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Herschel A. Ainspan, Mark A. Ferriss, Daniel J. Friedman, Alexander V. Rylyakov, Bodhisatwa Sadhu, Alberto Valdes-Garcia
  • Patent number: 9818058
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20170272125
    Abstract: RFID (radio frequency identification) systems are provided in which tag and interrogator devices implement a hybrid framework for signaling including an optical transmitter/receiver system and an RF transmitter/receiver system. For instance, an RFID tag device includes: optical receiver circuitry configured to receive an optical signal having an embedded clock signal from an interrogator device, and convert the optical signal into an electrical signal comprising the embedded clock signal; clock extraction circuitry configured to extract the embedded clock signal from the electrical signal, and output the extracted clock signal as a clock signal for controlling clocking functions of the tag device; voltage regulator circuitry configured to generate a regulated supply voltage from the electrical signal, wherein the regulated supply voltage is utilized as a bias voltage for components of the tag device; and data transmitter circuitry configured to wirelessly transmit tag data to the interrogator device.
    Type: Application
    Filed: June 7, 2017
    Publication date: September 21, 2017
    Inventors: Daniel J. Friedman, Duixian Liu, Mihai A. Sanduleanu
  • Patent number: 9755701
    Abstract: RFID (radio frequency identification) systems are provided in which tag and interrogator devices implement a hybrid framework for signaling including an optical transmitter/receiver system and an RF transmitter/receiver system. For instance, an RFID tag device includes: optical receiver circuitry configured to receive an optical signal having an embedded clock signal from an interrogator device, and convert the optical signal into an electrical signal comprising the embedded clock signal; clock extraction circuitry configured to extract the embedded clock signal from the electrical signal, and output the extracted clock signal as a clock signal for controlling clocking functions of the tag device; voltage regulator circuitry configured to generate a regulated supply voltage from the electrical signal, wherein the regulated supply voltage is utilized as a bias voltage for components of the tag device; and data transmitter circuitry configured to wirelessly transmit tag data to the interrogator device.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Friedman, Duixian Liu, Mihai A. Sanduleanu
  • Patent number: 9734371
    Abstract: RFID (radio frequency identification) systems are provided in which tag and interrogator devices implement a hybrid framework for signaling including an optical transmitter/receiver system and an RF transmitter/receiver system. For instance, an RFID tag device includes: optical receiver circuitry configured to receive an optical signal having an embedded clock signal from an interrogator device, and convert the optical signal into an electrical signal comprising the embedded clock signal; clock extraction circuitry configured to extract the embedded clock signal from the electrical signal, and output the extracted clock signal as a clock signal for controlling clocking functions of the tag device; voltage regulator circuitry configured to generate a regulated supply voltage from the electrical signal, wherein the regulated supply voltage is utilized as a bias voltage for components of the tag device; and data transmitter circuitry configured to wirelessly transmit tag data to the interrogator device.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Friedman, Duixian Liu, Mihai A. Sanduleanu
  • Patent number: 9735732
    Abstract: An apparatus includes an oscillation ring comprising N oscillators, where N is an even integer that is greater than 3, the N oscillators connected in series in a loop by N connection nodes, each oscillator of the N oscillators comprising a pair of cross-coupled inverting amplifiers. The apparatus also includes N inductors arranged in a star configuration such that each inductor of the N inductors connects to a corresponding connection node of the oscillation ring and a common connection node of the star configuration. The apparatus may also include N capacitor banks. Each of the N capacitor banks may include a plurality of activation switches for loading a corresponding oscillator with capacitance. A method includes providing the above apparatus and activating selected activation switches to adjust an oscillation frequency for the oscillation ring toward a desired value.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Ferriss, Daniel J. Friedman, Wooram Lee, Bodhisatwa Sadhu, Alberto Valdes Garcia
  • Publication number: 20170228568
    Abstract: RFID (radio frequency identification) systems are provided in which tag and interrogator devices implement a hybrid framework for signaling including an optical transmitter/receiver system and an RF transmitter/receiver system. For instance, an RFID tag device includes: optical receiver circuitry configured to receive an optical signal having an embedded clock signal from an interrogator device, and convert the optical signal into an electrical signal comprising the embedded clock signal; clock extraction circuitry configured to extract the embedded clock signal from the electrical signal, and output the extracted clock signal as a clock signal for controlling clocking functions of the tag device; voltage regulator circuitry configured to generate a regulated supply voltage from the electrical signal, wherein the regulated supply voltage is utilized as a bias voltage for components of the tag device; and data transmitter circuitry configured to wirelessly transmit tag data to the interrogator device.
    Type: Application
    Filed: April 26, 2017
    Publication date: August 10, 2017
    Inventors: Daniel J. Friedman, Duixian Liu, Mihai A. Sanduleanu
  • Publication number: 20170201215
    Abstract: A method includes forming a resonator comprising a plurality of switched impedances spatially distributed within the resonator, selecting a resonant frequency for the resonator, and distributing two or more transconductance elements within the resonator based on the selected resonant frequency. Distributing the two or more transconductance elements may include non-uniformly distributing the two or more transconductance elements within the resonator.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 13, 2017
    Inventors: Mark A. Ferriss, Daniel J. Friedman, Alexander V. Rylyakov, Bodhisatwa Sadhu, Alberto Valdes Garcia
  • Patent number: 9537224
    Abstract: Systems, methods, devices and apparatuses directed to transceiver devices are disclosed. In accordance with one method, a first set of antenna positions in a first section of a set of sections of a circuit layout for the circuit package is selected. The method further includes selecting another set of antenna positions in another section of the circuit layout such that an arrangement of selected antenna positions of the other set is different from an arrangement of selected antenna positions of a previously selected set of antenna positions. The selecting another set of positions in another section is iterated until selections have been made for a total number of antennas. The selecting the other set is performed such that consecutive unselected positions in the other section do not exceed a predetermined number of positions. In addition, antenna elements are formed at the selected positions to fabricate the circuit package.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Friedman, Xiaoxiong Gu, Duixian Liu, Arun S. Natarajan, Scott K. Reynolds, Alberto Valdes Garcia
  • Publication number: 20160358067
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Application
    Filed: August 22, 2016
    Publication date: December 8, 2016
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20160292470
    Abstract: RFID (radio frequency identification) systems are provided in which tag and interrogator devices implement a hybrid framework for signaling including an optical transmitter/receiver system and an RF transmitter/receiver system. For instance, an RFID tag device includes: optical receiver circuitry configured to receive an optical signal having an embedded clock signal from an interrogator device, and convert the optical signal into an electrical signal comprising the embedded clock signal; clock extraction circuitry configured to extract the embedded clock signal from the electrical signal, and output the extracted clock signal as a clock signal for controlling clocking functions of the tag device; voltage regulator circuitry configured to generate a regulated supply voltage from the electrical signal, wherein the regulated supply voltage is utilized as a bias voltage for components of the tag device; and data transmitter circuitry configured to wirelessly transmit tag data to the interrogator device.
    Type: Application
    Filed: June 25, 2015
    Publication date: October 6, 2016
    Inventors: Daniel J. Friedman, Duixian Liu, Mihai A. Sanduleanu
  • Publication number: 20160292569
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Application
    Filed: June 14, 2016
    Publication date: October 6, 2016
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20160294481
    Abstract: RFID (radio frequency identification) systems are provided in which tag and interrogator devices implement a hybrid framework for signaling including an optical transmitter/receiver system and an RF transmitter/receiver system. For instance, an RFID tag device includes: optical receiver circuitry configured to receive an optical signal having an embedded clock signal from an interrogator device, and convert the optical signal into an electrical signal comprising the embedded clock signal; clock extraction circuitry configured to extract the embedded clock signal from the electrical signal, and output the extracted clock signal as a clock signal for controlling clocking functions of the tag device; voltage regulator circuitry configured to generate a regulated supply voltage from the electrical signal, wherein the regulated supply voltage is utilized as a bias voltage for components of the tag device; and data transmitter circuitry configured to wirelessly transmit tag data to the interrogator device.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 6, 2016
    Inventors: Daniel J. Friedman, Duixian Liu, Mihai A. Sanduleanu
  • Patent number: 9460383
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: October 4, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20160285417
    Abstract: A voltage controlled oscillator comprises a negative resistance, a first inductor, a fixed capacitor, and a frequency control component. The frequency control component comprises at least one varactor and at least a second inductor connected in series with the at least one varactor. A magnitude of an inductance of the second inductor is selected such that the frequency control component has an effective capacitance range larger than a capacitance range of the at least one varactor.
    Type: Application
    Filed: May 11, 2016
    Publication date: September 29, 2016
    Inventors: Mark A. Ferriss, Daniel J. Friedman, Bodhisatwa Sadhu, Alberto Valdes-Garcia
  • Publication number: 20160260008
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.
    Type: Application
    Filed: May 13, 2016
    Publication date: September 8, 2016
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20160247063
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Application
    Filed: September 2, 2014
    Publication date: August 25, 2016
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-Sun Seo, Jose A. Tierno
  • Publication number: 20160224887
    Abstract: Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor.
    Type: Application
    Filed: January 7, 2016
    Publication date: August 4, 2016
    Inventors: Daniel J. Friedman, Seongwon Kim, Chung H. Lam, Dharmendra S. Modha, Bipin Rajendran, Jose A. Tierno
  • Publication number: 20160224890
    Abstract: Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor.
    Type: Application
    Filed: January 7, 2016
    Publication date: August 4, 2016
    Inventors: Daniel J. Friedman, Seongwon Kim, Chung H. Lam, Dharmendra S. Modha, Bipin Rajendran, Jose A. Tierno