Patents by Inventor Daniel J. Friedman

Daniel J. Friedman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10367513
    Abstract: A phase-locked loop circuit includes an oscillator, a frequency control device, the frequency control device generating a frequency control signal that controls a frequency of the oscillator, and a bias optimizer that monitors the frequency control device and generates a bias voltage for the oscillator, the oscillator includes a transfer function from bias voltage to frequency that is proportional to a transfer function from a low frequency noise component to frequency, the transfer function from bias voltage to frequency having a convex shape with a local minimum at which a sensitivity of the frequency to changes in the bias voltage is zero, and the bias voltage from the bias optimizer is set to the local minimum.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Ferriss, Daniel J. Friedman, Bodhisatwa Sadhu, Wooram Lee
  • Publication number: 20190228289
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Patent number: 10331998
    Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
  • Publication number: 20190165796
    Abstract: A phase-locked loop circuit includes an oscillator, a frequency control device, the frequency control device generating a frequency control signal that controls a frequency of the oscillator, and a bias optimizer that monitors the frequency control device and generates a bias voltage for the oscillator, the oscillator includes a transfer function from bias voltage to frequency that is proportional to a transfer function from a low frequency noise component to frequency, the transfer function from bias voltage to frequency having a convex shape with a local minimum at which a sensitivity of the frequency to changes in the bias voltage is zero, and the bias voltage from the bias optimizer is set to the local minimum.
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventors: Mark A. Ferriss, Daniel J. Friedman, Bodhisatwa Sadhu, Wooram Lee
  • Patent number: 10255467
    Abstract: RFID (radio frequency identification) systems are provided in which tag and interrogator devices implement a hybrid framework for signaling including an optical transmitter/receiver system and an RF transmitter/receiver system. For instance, an RFID tag device includes: optical receiver circuitry configured to receive an optical signal having an embedded clock signal from an interrogator device, and convert the optical signal into an electrical signal comprising the embedded clock signal; clock extraction circuitry configured to extract the embedded clock signal from the electrical signal, and output the extracted clock signal as a clock signal for controlling clocking functions of the tag device; voltage regulator circuitry configured to generate a regulated supply voltage from the electrical signal, wherein the regulated supply voltage is utilized as a bias voltage for components of the tag device; and data transmitter circuitry configured to wirelessly transmit tag data to the interrogator device.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Friedman, Duixian Liu, Mihai A. Sanduleanu
  • Patent number: 10211779
    Abstract: A voltage controlled oscillator comprises a negative resistance, a first inductor, a fixed capacitor, and a frequency control component. The frequency control component comprises at least one varactor and at least a second inductor connected in series with the at least one varactor. A magnitude of an inductance of the second inductor is selected such that the frequency control component has an effective capacitance range larger than a capacitance range of the at least one varactor.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Ferriss, Daniel J. Friedman, Bodhisatwa Sadhu, Alberto Valdes-Garcia
  • Patent number: 10090889
    Abstract: RFID (radio frequency identification) systems are provided in which tag and interrogator devices implement a hybrid framework for signaling including an optical transmitter/receiver system and an RF transmitter/receiver system. For instance, an RFID tag device includes: optical receiver circuitry configured to receive an optical signal having an embedded clock signal from an interrogator device, and convert the optical signal into an electrical signal comprising the embedded clock signal; clock extraction circuitry configured to extract the embedded clock signal from the electrical signal, and output the extracted clock signal as a clock signal for controlling clocking functions of the tag device; voltage regulator circuitry configured to generate a regulated supply voltage from the electrical signal, wherein the regulated supply voltage is utilized as a bias voltage for components of the tag device; and data transmitter circuitry configured to wirelessly transmit tag data to the interrogator device.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: October 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Friedman, Duixian Liu, Mihai A. Sanduleanu
  • Publication number: 20180232005
    Abstract: Aspects include a method for generating a signal in response to an event. The method includes receiving, from a clock signal generator, a clock signal, wherein the clock signal has a fixed clock period. The method further includes receiving an indication of a pulse and, responsive to receiving the indication of the pulse, generating an output comprising a high voltage having a starting time and an ending time. The starting time is a first time when the indication of the asynchronous event is received, and the ending time is a second time at one fixed clocked period from the starting time.
    Type: Application
    Filed: November 1, 2016
    Publication date: August 16, 2018
    Inventors: DANIEL J. FRIEDMAN, SEONGWON KIM, BIPIN RAJENDRAN
  • Publication number: 20180197073
    Abstract: One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Inventors: Daniel J. Friedman, Seongwon Kim, Chung H. Lam, Dharmendra S. Modha, Bipin Rajendran, Jose A. Tierno
  • Publication number: 20180197074
    Abstract: One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Inventors: Daniel J. Friedman, Seongwon Kim, Chung H. Lam, Dharmendra S. Modha, Bipin Rajendran, Jose A. Tierno
  • Publication number: 20180189530
    Abstract: RFID (radio frequency identification) systems are provided in which tag and interrogator devices implement a hybrid framework for signaling including an optical transmitter/receiver system and an RF transmitter/receiver system. For instance, an RFID tag device includes: optical receiver circuitry configured to receive an optical signal having an embedded clock signal from an interrogator device, and convert the optical signal into an electrical signal comprising the embedded clock signal; clock extraction circuitry configured to extract the embedded clock signal from the electrical signal, and output the extracted clock signal as a clock signal for controlling clocking functions of the tag device; voltage regulator circuitry configured to generate a regulated supply voltage from the electrical signal, wherein the regulated supply voltage is utilized as a bias voltage for components of the tag device; and data transmitter circuitry configured to wirelessly transmit tag data to the interrogator device.
    Type: Application
    Filed: February 26, 2018
    Publication date: July 5, 2018
    Inventors: DANIEL J. FRIEDMAN, Duixian Liu, Mihai A. Sanduleanu
  • Publication number: 20180181774
    Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
  • Patent number: 10007819
    Abstract: RFID (radio frequency identification) systems are provided in which tag and interrogator devices implement a hybrid framework for signaling including an optical transmitter/receiver system and an RF transmitter/receiver system. For instance, an RFID tag device includes: optical receiver circuitry configured to receive an optical signal having an embedded clock signal from an interrogator device, and convert the optical signal into an electrical signal comprising the embedded clock signal; clock extraction circuitry configured to extract the embedded clock signal from the electrical signal, and output the extracted clock signal as a clock signal for controlling clocking functions of the tag device; voltage regulator circuitry configured to generate a regulated supply voltage from the electrical signal, wherein the regulated supply voltage is utilized as a bias voltage for components of the tag device; and data transmitter circuitry configured to wirelessly transmit tag data to the interrogator device.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Friedman, Duixian Liu, Mihai A. Sanduleanu
  • Patent number: 9998073
    Abstract: A voltage controlled oscillator comprises a negative resistance, a first inductor, a fixed capacitor, and a frequency control component. The frequency control component comprises at least one varactor and at least a second inductor connected in series with the at least one varactor. A magnitude of an inductance of the second inductor is selected such that the frequency control component has an effective capacitance range larger than a capacitance range of the at least one varactor.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Ferriss, Daniel J. Friedman, Bodhisatwa Sadhu, Alberto Valdes-Garcia
  • Publication number: 20180159203
    Abstract: Antenna package structures are provided to implement wireless communications packages. For example, an antenna package includes multilayer package substrate, a planar antenna array, antenna feed lines, and resistive transmission lines. The planar antenna array includes an array of active antenna elements and dummy antenna elements surrounding the array of active antenna elements. Each active antenna element is coupled to a corresponding one of the antenna feed lines, and each dummy antenna element is coupled to a corresponding one of the resistive transmission lines. Each resistive transmission line extends through the multilayer package substrate and is terminated in a same metallization layer of the multilayer package substrate.
    Type: Application
    Filed: December 3, 2016
    Publication date: June 7, 2018
    Inventors: Christian W. Baks, Daniel J. Friedman, Xiaoxiong Gu, Duixian Liu, Alberto Valdes Garcia, Joakim Hallin, Ola Ragnar Tageman
  • Patent number: 9953261
    Abstract: Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Friedman, Seongwon Kim, Chung H. Lam, Dharmendra S. Modha, Bipin Rajendran, Jose A. Tierno
  • Patent number: 9954486
    Abstract: An apparatus comprises a digitally controlled circuit having a variable capacitance and a controller configured to adjust a magnitude of the variable capacitance of the digitally controlled circuit. The digitally controlled circuit comprises a plurality of gain elements, the plurality of gain elements comprising one or more positive voltage-to-frequency gain elements and one or more negative voltage-to-frequency gain elements. The controller is configured to adjust the magnitude of the capacitance by adjusting the gain provided by respective ones of the gain elements in an alternating sequence of the positive voltage-to-frequency gain elements and the negative voltage-to-frequency gain elements.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Herschel A. Ainspan, Mark A. Ferriss, Daniel J. Friedman, Alexander V. Rylyakov, Bodhisatwa Sadhu, Alberto Valdes-Garcia
  • Patent number: 9946969
    Abstract: Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Friedman, Seongwon Kim, Chung H. Lam, Dharmendra S. Modha, Bipin Rajendran, Jose A. Tierno
  • Patent number: 9948235
    Abstract: A method includes forming a resonator comprising a plurality of switched impedances spatially distributed within the resonator, selecting a resonant frequency for the resonator, and distributing two or more transconductance elements within the resonator based on the selected resonant frequency. Distributing the two or more transconductance elements may include non-uniformly distributing the two or more transconductance elements within the resonator.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Ferriss, Daniel J. Friedman, Alexander V. Rylyakov, Bodhisatwa Sadhu, Alberto Valdes Garcia
  • Patent number: 9948236
    Abstract: A method includes forming a resonator comprising a plurality of switched impedances spatially distributed within the resonator, selecting a resonant frequency for the resonator, and distributing two or more transconductance elements within the resonator based on the selected resonant frequency. Distributing the two or more transconductance elements may include non-uniformly distributing the two or more transconductance elements within the resonator.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Ferriss, Daniel J. Friedman, Alexander V. Rylyakov, Bodhisatwa Sadhu, Alberto Valdes Garcia