Patents by Inventor Daniel Krebs
Daniel Krebs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128358Abstract: A transistor arrangement for power transistors with a fin structure. It is provided to lower the epitaxy layer of the transistor arrangements in an edge region surrounding the fin structure and to introduce shield implants and edge implants into the epitaxy layer after lowering.Type: ApplicationFiled: October 13, 2023Publication date: April 18, 2024Inventors: Daniel Krebs, Jens Baringhaus
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Publication number: 20240128342Abstract: A field-effect transistor. The field-effect transistor includes: an n-doped source layer, an n-doped drain layer, a channel layer located vertically between the n-doped source layer and the n-doped drain layer, and several gate trenches extending vertically from the n-doped source layer to the n-doped drain layer and adjoining the channel layer. A fin is respectively formed between each two gate trenches, wherein at least two of the fins have different widths. A method for production is also described.Type: ApplicationFiled: October 17, 2023Publication date: April 18, 2024Inventors: Daniel Krebs, Jens Baringhaus
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Publication number: 20240128372Abstract: A method for manufacturing a vertical field effect transistor structure and to a corresponding vertical field effect transistor structure. The vertical field effect transistor structure is provided with a semiconductor body having first and second connecting zones of a first conductivity type, a channel zone of the first or second conductivity type between the first and second connecting zone, a plurality of trenches extending into the semiconductor body, reaching into the first connecting zone from the second connecting zone through the channel zone and forming fins of the channel zone and the second connecting zone, a control electrode arranged in the trenches, the electrode being arranged adjacent to the channel zone and insulated from the semiconductor body, and a breakdown current path connected between the first and second connecting zones and parallel to the channel zone, the current path having least one p-n junction.Type: ApplicationFiled: October 13, 2023Publication date: April 18, 2024Inventors: Christian Huber, Daniel Krebs
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Publication number: 20240097017Abstract: A semiconductor component designed as a vertical HEMT. The semiconductor component includes a substrate made of gallium nitride (GaN), a drift layer arranged thereon, and a heteroepitaxial structure which is arranged thereabove, is laterally contacted by source electrodes and is suitable for providing a conductive channel by forming a two-dimensional electron gas.Type: ApplicationFiled: September 13, 2023Publication date: March 21, 2024Inventors: Jens Baringhaus, Christian Huber, Daniel Krebs
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Publication number: 20240055528Abstract: A vertical field-effect transistor. The transistor includes: a drift region having a first conductivity type; a semiconductor fin on or over the drift region; and a source/drain electrode on or over the semiconductor fin, the semiconductor fin having an electrically conductive region that connects the source/drain electrode to the drift region in electrically conductive fashion, and having a limiting structure that is formed laterally next to the electrically conductive region and that extends from the source/drain electrode to the drift region, the limiting structure being set up to limit a conductive channel of the vertical field-effect transistor in the semiconductor fin to the area of the electrically conductive region.Type: ApplicationFiled: September 21, 2020Publication date: February 15, 2024Inventors: Jens Baringhaus, Daniel Krebs, Dick Scholten
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Publication number: 20230402538Abstract: A vertical semiconductor component. The component includes: a drift region having a first conductivity type; a trench structure on or above the drift region, a shielding structure situated laterally next to at least one sidewall of the trench structure on or above the drift region and having a second conductivity type, and the shielding structure having at least a part of a shielding structure-trench structure such that the shielding structure has at least a first region having a first thickness and a second region having a second thickness, and an edge termination structure on or above the drift region and having the second conductivity type, and the shielding structure having a first doping degree, and the edge termination structure having a second doping degree; and at least in the second region of the shielding structure, the edge termination structure being situated between the drift region and the shielding structure.Type: ApplicationFiled: November 17, 2021Publication date: December 14, 2023Inventors: Alberto Martinez-Limia, Daniel Krebs, Stephan Schwaiger, Wolfgang Feiler
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Publication number: 20230118158Abstract: A vertical fin field-effect transistor. The transistor has a semiconductor fin, an n-doped source region, an n-doped drift region, an n-doped channel region in the semiconductor fin situated vertically between the source region and the drift region, a gate region horizontally adjacent to the channel region, a gate dielectric electrically insulating the gate region from the channel region, a boundary surface between the gate dielectric and the channel region having negative boundary surface charges, a p-doped gate shielding region situated below the gate region so that, given the vertical projection, the gate shielding region is situated within a surface limited by the gate dielectric, a source contact electrically conductively connected to the source region, and an electrically conductive region between the gate region and the p-doped gate shielding region. The p-doped gate shielding region is electrically conductively connected to the source contact by the electrically conductive region.Type: ApplicationFiled: February 15, 2021Publication date: April 20, 2023Inventors: Daniel Krebs, Joachim Rudhard, Alberto Martinez-Limia, Jens Baringhaus, Wolfgang Feiler
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Publication number: 20230019288Abstract: A MOSFET with saturation contact. The MOSFET with saturation contact includes an n-doped source region, a source contact, a contact structure, which extends from the source contact to the n-doped source region, and forms with the source contact a first conductive connection and forms with the n-doped source region a second conductive connection, a barrier layer and an insulating layer. The contact structure includes a section between the first conductive connection and the second conductive connection, which is embedded between the barrier layer and the dielectric layer and is configured in such a way that a two-dimensional electron gas is formed therein.Type: ApplicationFiled: February 15, 2021Publication date: January 19, 2023Inventors: Jens Baringhaus, Daniel Krebs
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Publication number: 20220416028Abstract: A vertical field effect transistor. The vertical field effect transistor includes: a drift area including a first conductivity type; a semiconductor fin on or above the drift area, a source/drain electrode on or above the drift area; and a shielding structure, which is situated laterally adjacent to the at least one side wall of the semiconductor fin in the drift area, the shielding structure including a second conductivity type, which differs from the first conductivity type, and the semiconductor fin being electrically conductively connected to the source/drain electrode.Type: ApplicationFiled: September 21, 2020Publication date: December 29, 2022Inventors: Jens Baringhaus, Daniel Krebs, Dick Scholten
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Publication number: 20220367713Abstract: A vertical field effect transistor. The vertical field effect transistor includes: a drift area; a semiconductor fin on or above the drift area; a connection area on or above the semiconductor fin; and a gate electrode, which is formed adjacent to at least one side wall of the semiconductor fin, the semiconductor fin, in a first section, which is situated laterally adjacent to the gate electrode, having a lesser lateral extension than in a second section, which contacts the drift area, and/or than in a third section, which contacts the connection area.Type: ApplicationFiled: September 24, 2020Publication date: November 17, 2022Inventors: Jens Baringhaus, Daniel Krebs, Dick Scholten
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Publication number: 20220231120Abstract: A transistor cell including a semiconductor substrate, which has a front side and a rear side, the front side being situated opposite the rear side. An epitaxial layer is situated on the front side. Channel regions are situated on the epitaxial layer. Source regions are situated on the channel regions. A trench and field shielding regions extending from the front side of the semiconductor substrate into the epitaxial layer, the field shielding regions each being situated laterally spaced apart from the trench and the trench having a shallower depth than the field shielding regions. An implanted expansion region having a particular thickness is situated below the trench.Type: ApplicationFiled: May 18, 2020Publication date: July 21, 2022Inventors: Alberto Martinez-Limia, Stephan Schwaiger, Daniel Krebs, Dick Scholten, Holger Bartolf, Jan-Hendrik Alsmeier, Wolfgang Feiler
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Patent number: 9570679Abstract: A semiconductor structure is described containing a deflector between a first nanoscale device and a second nanoscale device. The deflector is designed to deflect near-field radiation from emanating from the first nanoscale device to the second nanoscale device. In some embodiments, this may be accomplished using at least one nanoscale element located between the first and second nanoscale device, where the nanoscale element is tuned to the proper plasmon-polariton frequency to deflect the near field radiation.Type: GrantFiled: July 17, 2014Date of Patent: February 14, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Daniel Krebs, Gabriele Raino
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Patent number: 9548110Abstract: A memory device for thermoelectric heat confinement and method for producing same. The memory device includes a plurality of phase-change memory cells, wherein each of the phase-change memory cells has a first electrode, a second electrode and a phase-change material. The first electrode and the phase-change material are arranged such that a surface normal of a dominating interface for a current flow between the first electrode and the phase-change material points on one side to the phase-change material of the phase-change memory cell and on an opposite side to a phase-change material of a neighboring phase-change memory cell. A method for producing a memory device for thermoelectric heat confinement is also provided.Type: GrantFiled: August 6, 2015Date of Patent: January 17, 2017Assignee: International Business Machines CorporationInventors: Aravinthan Athmanathan, Daniel Krebs
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Patent number: 9530493Abstract: Improved random-access memory cells, complementary cells, and memory devices. The present invention provides a RRAM cell for storing information in a plurality of programmable cell states. The RRAM cell includes: an electrically-insulating matrix located between a first electrode and a second electrode such that an electrically-conductive path, extending in a direction between said electrodes, is formed within said matrix on application of a write voltage to said electrodes; an electrically-conductive component; wherein a resistance is presented by the electrically-conductive component; and wherein said RRAM is arranged such that said resistance is at least about that of said electrically-conductive path and at most about that of said electrically-insulating matrix in any of said plurality of programmable cell states.Type: GrantFiled: March 15, 2016Date of Patent: December 27, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Evangelos S Eleftheriou, Daniel Krebs, Abu Sebastian
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Publication number: 20160196874Abstract: Improved random-access memory cells, complementary cells, and memory devices. The present invention provides a RRAM cell for storing information in a plurality of programmable cell states. The RRAM cell includes: an electrically-insulating matrix located between a first electrode and a second electrode such that an electrically-conductive path, extending in a direction between said electrodes, is formed within said matrix on application of a write voltage to said electrodes; an electrically-conductive component; wherein a resistance is presented by the electrically-conductive component; and wherein said RRAM is arranged such that said resistance is at least about that of said electrically-conductive path and at most about that of said electrically-insulating matrix in any of said plurality of programmable cell states.Type: ApplicationFiled: March 15, 2016Publication date: July 7, 2016Inventors: EVANGELOS S ELEFTHERIOU, DANIEL KREBS, ABU SEBASTIAN
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Publication number: 20160104529Abstract: A memory device for thermoelectric heat confinement and method for producing same. The memory device includes a plurality of phase-change memory cells, wherein each of the phase-change memory cells has a first electrode, a second electrode and a phase-change material. The first electrode and the phase-change material are arranged such that a surface normal of a dominating interface for a current flow between the first electrode and the phase-change material points on one side to the phase-change material of the phase-change memory cell and on an opposite side to a phase-change material of a neighboring phase-change memory cell. A method for producing a memory device for thermoelectric heat confinement is also provided.Type: ApplicationFiled: August 6, 2015Publication date: April 14, 2016Inventors: Aravinthan Athmanathan, Daniel Krebs
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Patent number: 9305636Abstract: Improved random-access memory cells, complementary cells, and memory devices. RRAM cells are provided for storing information in a plurality of programmable cell states. An electrically-insulating matrix is located between first and second electrodes such that an electrically-conductive path, which extends in a direction between the electrodes, can be formed within the matrix on application of a write voltage to the electrodes. The programmable cell states correspond to respective configurations of the conductive path in the matrix. An electrically-conductive component extends in a direction between the electrodes in contact with the insulating matrix. The arrangement is such that the resistance presented by the component to a cell current produced by a read voltage applied to the electrodes to read the programmed cell state is at least about that of the conductive path and at most about that of the insulating matrix in any of the cell states.Type: GrantFiled: June 16, 2014Date of Patent: April 5, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Evangelos S Eleftheriou, Daniel Krebs, Abu Sebastian
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Patent number: 9293199Abstract: A phase-change memory cell for storing information in a plurality of programmable cell states. The memory cell includes: a phase-change material located between a first electrode and a second electrode for applying a read voltage to the phase-change material to read a programmed cell state; and an electrically-conductive component extending in a direction between the first and second electrodes in contact with the phase-change material and arranged to present, to a cell current produced by the read voltage, a lower-resistance current path than an amorphous phase of the phase-change material in any of the plurality of programmable cell states, said current path having a length dependent on a size of said amorphous phase, wherein a volume of the electrically-conductive component is greater than about half that of said phase-change material.Type: GrantFiled: June 5, 2014Date of Patent: March 22, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Daniel Krebs, Abu Sebastian
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Patent number: 9293198Abstract: A method for programming gated phase-change memory cells, each with a gate, source and drain, having s?2 programmable cell-states including an amorphous RESET state and at least one crystalline state includes applying a programming signal between the source and drain of a memory cell to program that cell to a desired cell-state; and when programming the cell from a crystalline state to the RESET state, applying a bias voltage to the gate of the cell to increase the cell resistance.Type: GrantFiled: May 22, 2013Date of Patent: March 22, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Daniel Krebs
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Patent number: 9257639Abstract: Improved phase-change memory cells are provided for storing information in a plurality of programmable cell states. A phase-change material is located between first and second electrodes for applying a read voltage to the phase-change material to read the programmed cell state. An electrically-conductive component extends from one electrode to the other in contact with the phase-change material. The resistance presented by this component to a cell current produced by the read voltage is less than that of the amorphous phase and greater than that of the crystalline phase of the phase-change material in any of the cell states.Type: GrantFiled: June 5, 2014Date of Patent: February 9, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: SangBum Kim, Daniel Krebs, Chung Hon Lam, Charalampos Pozidis