Abstract: A method for producing power FinFETs with one-piece control electrodes. The method includes: creating a first structured mask; creating first trenches below first open regions by a first etching process starting from the front side of the semiconductor body and extending into the drift layer; creating shielding regions below the first trenches by a first implantation process; applying an isotropic oxide layer to the front side of the semiconductor body; creating a second structured mask; creating second trenches below second open regions by a third etching process; oxidizing the front side such that a further oxide layer is disposed on the front side; widening the first trenches and the second trenches by a fourth etching process; applying a polysilicon layer to the front side of the semiconductor body such that the first trenches and the second trenches are completely filled; and activating the shielding regions by means of annealing.

Abstract: A method for manufacturing a vertical field effect transistor structure and a vertical field effect transistor structure. The vertical field effect transistor structure has a semiconductor body having first and second connection zones of a first conductor type, a channel zone of the first conductor type, or of a second conductor type complementary to the first conductor type, arranged between the first and second connection zone, a plurality of trenches extending into the semiconductor body, the trenches reaching from the second connection zone through the channel zone into the first connection zone and forming fins of the channel zone and of the second connection zone, a control electrode arranged in the trenches, the electrode being arranged adjacent to the channel zone and insulated from the semiconductor body, and a breakdown current path connected between the first and second connection zones and in parallel with the channel zone.

Abstract: A method for producing a power semiconductor component having a plurality of fins. The method includes: creating a plurality of mesas starting from a front side of a semiconductor substrate into a drift layer of the semiconductor substrate by means of etching, each mesa being arranged between a first trench and a second trench. Each mesa has a width greater than 500 nm. The method further includes applying a mask layer to the top side, the first side surface, the second side surface, the first trench bottom surface and the second trench bottom surface; creating a structured mask by removing the mask layer in certain regions, so that an exposed surface is created; creating fins by machining the exposed surface; removing the structured mask and completing the power semiconductor component.

Abstract: A method for producing a power FinFET with two-part control electrodes. The method includes: creating a first structured mask including oxide regions and first and second open regions on the front side of a semiconductor body via lithography; creating first and second trenches below the first and second open regions, respectively, by a first etching process starting from the front side of the semiconductor body into the drift layer, the first and second trenches being arranged substantially parallel to one another and alternate, the second trenches have a smaller width than the first trenches; applying a polysilicon layer onto the front side so that the first and second trenches are filled; applying an isotropic oxide layer onto the front side of the semiconductor body; creating a second structured mask on the isotropic oxide layer via lithography, wherein the second structured mask is open above the first trenches.

Abstract: A method for producing a power FinFET with two-part control electrodes. The power FinFET includes a semiconductor body, which includes a first connection region, a drift layer, a channel region and a second connection region. The method includes producing trenches, which extend from the second connection region into the drift layer, the trenches being arranged substantially in parallel with one another; producing shielding regions below the trenches using an implantation process, so that a shielding region is arranged below each trench; widening the trenches using at least one etching process, so that fins are formed between the trenches, the fins having a width of less than 500 nm; and producing the two-part control electrodes, which are arranged within the trenches, so that one two-part control electrode is in each case arranged in each trench. Each two-part control electrode is electrically insulated from the shielding region below the trench.

Abstract: A power finFET. The power finFET has two-part control electrodes and a semiconductor body which has a drift layer, and a second connection region arranged above the drift layer. The first trenches and second trenches extend from the second connection region into the drift layer, and being arranged in an alternating manner, the second trenches having a smaller width than the first trenches. Shielding zones are arranged below the first trenches, the shielding zones directly adjoining the first trenches, and the shielding zones being connected to source regions in an electrically conductive manner. A two-part control electrode is arranged within the first trenches in each case, the two-part control electrode being electrically insulated from the shielding zone below the first trenches in each case. Fins are arranged between the first trenches and the second trenches, the fins having a width of at most 500 nm.

Abstract: A vertical field-effect transistor. The transistor includes: a drift region having a first conductivity type; a semiconductor fin on or over the drift region; and a source/drain electrode on or over the semiconductor fin, the semiconductor fin having an electrically conductive region that connects the source/drain electrode to the drift region in electrically conductive fashion, and having a limiting structure that is formed laterally next to the electrically conductive region and that extends from the source/drain electrode to the drift region, the limiting structure being set up to limit a conductive channel of the vertical field-effect transistor in the semiconductor fin to the area of the electrically conductive region.

Abstract: A field-effect transistor. The field-effect transistor includes: a source layer doped according to a first type, a drain layer doped according to a first type, a channel layer located vertically between the source layer doped according to a first type and the drain layer doped according to a first type, and, extending in particular horizontally, fins and gate trenches, wherein the fins and the gate trenches in each case extend in the vertical direction from the source layer doped according to a first type to the drain layer doped according to a first type, and wherein the gate trenches are in each case formed between two adjacent fins, wherein the field-effect transistor further includes a support structure for the fins.

Abstract: A vertical field-effect transistor structure. The vertical field-effect transistor structure has a semiconductor body having a first terminal zone, a drift zone, and a second terminal zone of a first conductivity type; a channel zone, arranged between the first and the second terminal zone, of the first or second conductivity type; a plurality of first trenches extending into the semiconductor body from the second terminal zone into the drift zone and form fins of the channel and second terminal zones; a control electrode arranged in the first trenches, which is arranged adjacent to the channel zone and insulated from the semiconductor body; a current path, connected between the first and the second terminal zone and in parallel with the channel zone, having at least one Schottky junction and being designed to conduct when a reverse voltage between the first and the second terminal zone is reached.

Abstract: A vertical field-effect transistor structure, and a method for producing the structure. The structure includes a semiconductor body having a first terminal zone, a drift zone, and a second terminal zone of a first conductivity type; a channel zone, between the first and the second terminal zone, of the first or second conductivity type; first trenches extending into the semiconductor body, which extend from the second terminal zone into the drift zone and form fins of the channel and second terminal zones; a control electrode arranged in the first trenches, adjacent to the channel zone and insulated from the semiconductor body; and a current path connected between the first and the second terminal zone and in parallel with the channel zone, the current path having at least one Schottky junction and which conducts when a reverse voltage between the first and the second terminal zones is reached.

Abstract: A field-effect transistor. The field-effect transistor includes: a source layer doped according to a first type, a drain layer doped according to a first type, a channel layer located vertically between the source layer doped according to the first type and the drain layer doped according to the first type, and a gate trench which extends vertically from the source layer doped according to the first type to the drift layer doped according to the first type and adjoins the channel layer. The channel layer has, at least on average, a lower doping of the second type and a higher doping of the first type in a region that is more than a specified distance from the gate trench than in a region that is less than the specified distance from the gate trench. Methods for production are also described.

Abstract: A vertical semiconductor component, in particular a vertical transistor. The component has a vertically lower drain electrode and a semiconductor layer structure arranged vertically above the drain electrode, the semiconductor layer structure having at least one drift layer and a trench-shaped conduction channel, wherein a vertically lower end region of the conduction channel adjoins the drift layer, and wherein a gate electrode is formed vertically above the conduction channel and the conduction channel is conductively connected to a source electrode. The conduction channel has, in an at least partially vertically extending wall portion, a gradation, which is delimited by an upper and a lower boundary surface of the conduction channel such that the wall portion has lateral outer and inner portions which are connected to one another via a lateral intermediate portion. The intermediate portion has a reduced cross-section compared with the outer and inner portions.

Abstract: A vertical field-effect transistor structure including a semiconductor body having a drift zone having a first doping of a first doping type, multiple first trenches, and multiple second trenches. The first trenches have at most a first trench depth, and the second trenches have at least a second trench depth. The second trench depth is at least 50 nm longer than the first trench depth. The structure includes a shielding region adjacent to each trench bottom of the first trenches, which has a second doping of a second doping type, and at least one gate electrode in each of the first and second trenches, which is electrically insulated at least from the adjacent trench bottom and trench side wall. Each region adjacent to the trench bottoms of the second trenches has exclusively the first doping of the drift zone and is free from the second doping.

Abstract: A field-effect transistor. The field-effect transistor includes: a source layer doped according to a first type, a drain layer doped according to a first type, a channel layer located vertically between the source layer doped according to the first type and the drain layer doped according to the first type, and a gate trench which extends vertically from the source layer doped according to the first type to the drift layer doped according to the first type and adjoins the channel layer. The channel layer has, at least on average, a lower doping of the second type and a higher doping of the first type in a region that is more than a specified distance from the gate trench than in a region that is less than the specified distance from the gate trench. Methods for production are also described.

Abstract: A transistor arrangement for power transistors with a fin structure. It is provided to lower the epitaxy layer of the transistor arrangements in an edge region surrounding the fin structure and to introduce shield implants and edge implants into the epitaxy layer after lowering.

Abstract: A method for manufacturing a vertical field effect transistor structure and to a corresponding vertical field effect transistor structure. The vertical field effect transistor structure is provided with a semiconductor body having first and second connecting zones of a first conductivity type, a channel zone of the first or second conductivity type between the first and second connecting zone, a plurality of trenches extending into the semiconductor body, reaching into the first connecting zone from the second connecting zone through the channel zone and forming fins of the channel zone and the second connecting zone, a control electrode arranged in the trenches, the electrode being arranged adjacent to the channel zone and insulated from the semiconductor body, and a breakdown current path connected between the first and second connecting zones and parallel to the channel zone, the current path having least one p-n junction.

Abstract: A field-effect transistor. The field-effect transistor includes: an n-doped source layer, an n-doped drain layer, a channel layer located vertically between the n-doped source layer and the n-doped drain layer, and several gate trenches extending vertically from the n-doped source layer to the n-doped drain layer and adjoining the channel layer. A fin is respectively formed between each two gate trenches, wherein at least two of the fins have different widths. A method for production is also described.

Abstract: A semiconductor component designed as a vertical HEMT. The semiconductor component includes a substrate made of gallium nitride (GaN), a drift layer arranged thereon, and a heteroepitaxial structure which is arranged thereabove, is laterally contacted by source electrodes and is suitable for providing a conductive channel by forming a two-dimensional electron gas.

Abstract: A vertical field-effect transistor. The transistor includes: a drift region having a first conductivity type; a semiconductor fin on or over the drift region; and a source/drain electrode on or over the semiconductor fin, the semiconductor fin having an electrically conductive region that connects the source/drain electrode to the drift region in electrically conductive fashion, and having a limiting structure that is formed laterally next to the electrically conductive region and that extends from the source/drain electrode to the drift region, the limiting structure being set up to limit a conductive channel of the vertical field-effect transistor in the semiconductor fin to the area of the electrically conductive region.

Abstract: A vertical semiconductor component. The component includes: a drift region having a first conductivity type; a trench structure on or above the drift region, a shielding structure situated laterally next to at least one sidewall of the trench structure on or above the drift region and having a second conductivity type, and the shielding structure having at least a part of a shielding structure-trench structure such that the shielding structure has at least a first region having a first thickness and a second region having a second thickness, and an edge termination structure on or above the drift region and having the second conductivity type, and the shielding structure having a first doping degree, and the edge termination structure having a second doping degree; and at least in the second region of the shielding structure, the edge termination structure being situated between the drift region and the shielding structure.