Abstract: A method for programming gated phase-change memory cells, each with a gate, source and drain, having s?2 programmable cell-states including an amorphous RESET state and at least one crystalline state includes applying a programming signal between the source and drain of a memory cell to program that cell to a desired cell-state; and when programming the cell from a crystalline state to the RESET state, applying a bias voltage to the gate of the cell to increase the cell resistance.

Abstract: Improved phase-change memory cells are provided for storing information in a plurality of programmable cell states. A phase-change material is located between first and second electrodes for applying a read voltage to the phase-change material to read the programmed cell state. An electrically-conductive component extends from one electrode to the other in contact with the phase-change material. The resistance presented by this component to a cell current produced by the read voltage is less than that of the amorphous phase and greater than that of the crystalline phase of the phase-change material in any of the cell states.

Abstract: Improved random-access memory cells, complementary cells, and memory devices. RRAM cells are provided for storing information in a plurality of programmable cell states. An electrically-insulating matrix is located between first and second electrodes such that an electrically-conductive path, which extends in a direction between the electrodes, can be formed within the matrix on application of a write voltage to the electrodes. The programmable cell states correspond to respective configurations of the conductive path in the matrix. An electrically-conductive component extends in a direction between the electrodes in contact with the insulating matrix. The arrangement is such that the resistance presented by the component to a cell current produced by a read voltage applied to the electrodes to read the programmed cell state is at least about that of the conductive path and at most about that of the insulating matrix in any of the cell states.

Abstract: A device for determining an actual level of a resistive memory cell having a plurality of programmable levels is suggested. The device comprises an estimator unit and a detection unit. The estimator unit is adapted to receive a time input signal and a temperature input signal and to estimate changes of a read-out signal of the levels of the resistive memory cell based on a time and temperature dependent model of the resistance changes, the received time input signal and the received temperature input signal. The detection unit is adapted to receive an actual read-out signal from the resistive memory cell and the estimated changes from the estimator unit. Further, the detection unit is adapted to determine the actual level of the resistive memory cell based on the received read-out signal and the received estimated changes.

Abstract: Phase-change memory cells for storing information in a plurality of programmable cell states. A phase-change component is located between first and second electrodes for applying a read voltage to the phase-change component to read the programmed cell state. The component includes opposed layers of phase-change material extending between the electrodes. A core component extends between the electrodes in contact with respective inner surfaces of the opposed layers. An outer component extends between the electrodes in contact with respective outer surfaces of the opposed layers. At least one of the core and outer component is formed of electrically-conductive material and is arranged to present, to a cell current produced by the read voltage, a lower-resistance current path than the amorphous phase of the phase-change material in any of said cell states. The current path has a length dependent on size of the amorphous phase in the opposed layers.

Abstract: A memory apparatus includes a plurality of gated phase-change memory cells having s?2 programmable cell-states, the cells each having a gate and being arranged in series between a source and drain; a bias voltage generator configured to apply a bias voltage to the gate of each cell; and a controller configured to control the bias voltage generator, in a write operation for programming the state of a cell, to apply a first bias voltage to the gate of each cell except an addressed cell for the write operation, wherein application of the first bias voltage to a cell reduces the cell resistance such that application of a programming signal between the source and drain effects programming of the addressed cell only.

Abstract: A memory apparatus includes a plurality of gated phase-change memory cells having s?2 programmable cell-states, the cells each having a gate and being arranged in series between a source and drain; a bias voltage generator configured to apply a bias voltage to the gate of each cell; and a controller configured to control the bias voltage generator, in a write operation for programming the state of a cell, to apply a first bias voltage to the gate of each cell except an addressed cell for the write operation, wherein application of the first bias voltage to a cell reduces the cell resistance such that application of a programming signal between the source and drain effects programming of the addressed cell only.

Abstract: A semiconductor stack for performing at least a logic operation includes adjacent layers arranged in a stacked configuration with each layer comprising at least a phase-change memory cell in which a phase-change material is provided between a heater electrical terminal and at least two further heater electrical terminals, the phase-change material between the heater electrical terminal and each of the two further heater electrical terminals being operable in one of at least two reversibly transformable phases, an amorphous phase and a crystalline phase; wherein the semiconductor stack, when in use, is configurable to store information by way of an electrical resistance of the phase of the phase-change material between each heater electrical terminal and each of the two further heater electrical terminals in each layer, and the logic operation is performed on the basis of the information stored in the adjacent layers.

Abstract: A phase-change memory cell includes a phase change material; a reference electrical terminal disposed on first side of the phase change material; first and second electrical terminals disposed on a second side of the phase change material; the phase-change material configured to be reversibly transformable between an amorphous phase and a crystalline phase, in response to a phase-altering electrical signal applied to the phase-change material via the reference electrical terminal and one or more of the first and second electrical terminals; a resistance measurement unit configured to measure a respective electrical resistance between each of the first and electrical terminals and the reference electrical terminal; and a mathematical operation unit configured to determine a mathematical relation between the respective electrical resistances measured between each of the electrical terminals and the reference electrical terminal.

Abstract: A semiconductor structure is described containing a deflector between a first nanoscale device and a second nanoscale device. The deflector is designed to deflect near-field radiation from emanating from the first nanoscale device to the second nanoscale device. In some embodiments, this may be accomplished using at least one nanoscale element located between the first and second nanoscale device, where the nanoscale element is tuned to the proper plasmon-polariton frequency to deflect the near field radiation.

Abstract: A semiconductor stack for performing at least a logic operation includes adjacent layers arranged in a stacked configuration with each layer comprising at least a phase-change memory cell in which a phase-change material is provided between a heater electrical terminal and at least two further heater electrical terminals, the phase-change material between the heater electrical terminal and each of the two further heater electrical terminals being operable in one of at least two reversibly transformable phases, an amorphous phase and a crystalline phase; wherein the semiconductor stack, when in use, is configurable to store information by way of an electrical resistance of the phase of the phase-change material between each heater electrical terminal and each of the two further heater electrical terminals in each layer, and the logic operation is performed on the basis of the information stored in the adjacent layers.

Abstract: Phase-change memory cells for storing information in a plurality of programmable cell states. A phase-change component is located between first and second electrodes for applying a read voltage to the phase-change component to read the programmed cell state. The component includes opposed layers of phase-change material extending between the electrodes. A core component extends between the electrodes in contact with respective inner surfaces of the opposed layers. An outer component extends between the electrodes in contact with respective outer surfaces of the opposed layers. At least one of the core and outer component is formed of electrically-conductive material and is arranged to present, to a cell current produced by the read voltage, a lower-resistance current path than the amorphous phase of the phase-change material in any of said cell states. The current path has a length dependent on size of the amorphous phase in the opposed layers.

Abstract: Improved random-access memory cells, complementary cells, and memory devices. RRAM cells are provided for storing information in a plurality of programmable cell states. An electrically-insulating matrix is located between first and second electrodes such that an electrically-conductive path, which extends in a direction between the electrodes, can be formed within the matrix on application of a write voltage to the electrodes. The programmable cell states correspond to respective configurations of the conductive path in the matrix. An electrically-conductive component extends in a direction between the electrodes in contact with the insulating matrix. The arrangement is such that the resistance presented by the component to a cell current produced by a read voltage applied to the electrodes to read the programmed cell state is at least about that of the conductive path and at most about that of the insulating matrix in any of the cell states.

Abstract: A phase-change memory cell for storing information in a plurality of programmable cell states. The memory cell includes: a phase-change material located between a first electrode and a second electrode for applying a read voltage to the phase-change material to read a programmed cell state; and an electrically-conductive component extending in a direction between the first and second electrodes in contact with the phase-change material and arranged to present, to a cell current produced by the read voltage, a lower-resistance current path than an amorphous phase of the phase-change material in any of the plurality of programmable cell states, said current path having a length dependent on a size of said amorphous phase, wherein a volume of the electrically-conductive component is greater than about half that of said phase-change material.

Abstract: Improved phase-change memory cells are provided for storing information in a plurality of programmable cell states. A phase-change material is located between first and second electrodes for applying a read voltage to the phase-change material to read the programmed cell state. An electrically-conductive component extends from one electrode to the other in contact with the phase-change material. The resistance presented by this component to a cell current produced by the read voltage is less than that of the amorphous phase and greater than that of the crystalline phase of the phase-change material in any of the cell states.

Abstract: A semiconductor stack for performing at least a logic operation includes adjacent layers arranged in a stacked configuration with each layer comprising at least a phase-change memory cell in which a phase-change material is provided between a heater electrical terminal and at least two further heater electrical terminals, the phase-change material between the heater electrical terminal and each of the two further heater electrical terminals being operable in one of at least two reversibly transformable phases, an amorphous phase and a crystalline phase; wherein the semiconductor stack, when in use, is configurable to store information by way of an electrical resistance of the phase of the phase-change material between each heater electrical terminal and each of the two further heater electrical terminals in each layer, and the logic operation is performed on the basis of the information stored in the adjacent layers.

Abstract: A semiconductor stack for performing at least a logic operation includes adjacent layers arranged in a stacked configuration with each layer comprising at least a phase-change memory cell in which a phase-change material is provided between a heater electrical terminal and at least two further heater electrical terminals, the phase-change material between the heater electrical terminal and each of the two further heater electrical terminals being operable in one of at least two reversibly transformable phases, an amorphous phase and a crystalline phase; wherein the semiconductor stack, when in use, is configurable to store information by way of an electrical resistance of the phase of the phase-change material between each heater electrical terminal and each of the two further heater electrical terminals in each layer, and the logic operation is performed on the basis of the information stored in the adjacent layers.

Abstract: A memory apparatus includes a plurality of gated phase-change memory cells having s?2 programmable cell-states, the cells each having a gate and being arranged in series between a source and drain; a bias voltage generator configured to apply a bias voltage to the gate of each cell; and a controller configured to control the bias voltage generator, in a write operation for programming the state of a cell, to apply a first bias voltage to the gate of each cell except an addressed cell for the write operation, wherein application of the first bias voltage to a cell reduces the cell resistance such that application of a programming signal between the source and drain effects programming of the addressed cell only.

Abstract: A memory apparatus includes a plurality of gated phase-change memory cells having s?2 programmable cell-states, the cells each having a gate and being arranged in series between a source and drain; a bias voltage generator configured to apply a bias voltage to the gate of each cell; and a controller configured to control the bias voltage generator, in a write operation for programming the state of a cell, to apply a first bias voltage to the gate of each cell except an addressed cell for the write operation, wherein application of the first bias voltage to a cell reduces the cell resistance such that application of a programming signal between the source and drain effects programming of the addressed cell only.

Abstract: A method for programming gated phase-change memory cells, each with a gate, source and drain, having s?2 programmable cell-states including an amorphous RESET state and at least one crystalline state includes applying a programming signal between the source and drain of a memory cell to program that cell to a desired cell-state; and when programming the cell from a crystalline state to the RESET state, applying a bias voltage to the gate of the cell to increase the cell resistance.