Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache preload operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

Abstract: A silent chain includes a plurality of inner links, a plurality of outer links, and a plurality of rotation rods. The inner links are arranged along a transmission direction. At least one of the inner links includes an inner chain body that is made of a nonmetallic material and that has an engagement protrusion protruding in an engagement direction, and an inner plate unit that is disposed on an outer side of the inner chain body. The outer links are spaced apart from each other along the transmission direction and are disposed on outer sides of the inner links. The outer links and the inner links are disposed in an alternating arrangement along the transmission direction. The rotation rods interconnect the inner links and the outer links in series so that each of the inner links is rotatable relative to each of two adjacent ones of the outer links.

Abstract: A silent chain includes a plurality of inner links, a plurality of outer links, and a plurality of rotation rods. The inner links are arranged along a transmission direction. At least one of the inner links includes an inner plate unit, and an inner chain body that is fixedly disposed on an outer side of the inner plate unit, that is made of a nonmetallic material, and that has an engagement protrusion protruding in an engagement direction. The outer links are spaced apart from each other along the transmission direction and are disposed on outer sides of the inner links. The outer links and the inner links are disposed in an alternating arrangement along the transmission direction. The rotation rods interconnect the inner links and the outer links in series so that each of the inner links is rotatable relative to each of two adjacent ones of the outer links.

Abstract: A circuit includes a microcontroller having a first terminal and a second terminal. The microcontroller is configured to: receive a signal associated with operation of a power converter at the first terminal; adjust a switch control signal at the second terminal responsive to the signal; measure a frequency of the switch control signal; compare the measured frequency responsive to at least one envelope of a set of envelopes to obtain monitoring results; and perform control operations responsive to the monitoring results.

Abstract: The subject matter relates generally to performing polymerase chain reaction (PCR) in microfluidics devices and more particularly to a microfluidics system, device, and methods for performing rapid polymerase chain reaction (PCR) protocols. In some embodiments, the presently disclosed subject matter provides a microfluidics system including a microfluidics instrument housing a microfluidics cartridge (or device) along with any supporting components. Further, the microfluidics cartridge may be, for example, any fluidics device or cartridge, microfluidics device or cartridge, DMF device or cartridge, droplet actuator, flow cell device or cartridge, and the like.

Abstract: Methods, apparatus, and processor-readable storage media for artificial intelligence-based techniques for automated visual data searching using edge devices are provided herein. An example computer-implemented method includes obtaining visual data from one or more edge devices; generating at least one automated searching tool by processing at least a portion of the obtained data using one or more artificial intelligence techniques; deploying the at least one automated searching tool to at least a portion of the one or more edge devices; and performing one or more automated actions based at least in part on data received, from at least a portion of the one or more edge devices, in connection with operation of the at least one automated searching tool.

Abstract: A device includes a data path, a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address, and a controller connected to the data path and configured to receive the request to write the data value to the memory address and to calculate a Hamming code of the data value. The controller is configured to transmit the data value and the Hamming code on the data path. The device includes an external memory interleave connected to the data path. The external memory interleave is configured to receive the data value and calculate a test Hamming code of the data value and to determine whether to send the data value to an external memory interface to be written to the memory address based on a comparison of the Hamming code and the test Hamming code.

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.

Abstract: Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.

Abstract: The subject matter relates generally to performing polymerase chain reaction (PCR) in microfluidics devices and more particularly to a microfluidics system, device, and methods for performing rapid polymerase chain reaction (PCR) protocols. In some embodiments, the presently disclosed subject matter provides a microfluidics system including a microfluidics instrument housing a microfluidics cartridge (or device) along with any supporting components. Further, the microfluidics cartridge may be, for example, any fluidics device or cartridge, microfluidics device or cartridge, DMF device or cartridge, droplet actuator, flow cell device or cartridge, and the like.

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.

Abstract: An example apparatus includes: bandwidth estimator circuitry configured to: obtain a first memory transaction; and determine a consumed bandwidth associated with the memory transaction; and gate circuitry configured to: permit transmission of the memory transaction to a memory controller circuitry; determine whether to gate a second memory transaction generated by a source of the first memory transaction based on the consumed bandwidth of the first memory transaction; and when it is determined to gate the second memory transaction, prevent transmission of the second memory transaction for an amount of time based on the consumed bandwidth.

Abstract: A bag for storing cosmetic products comprising an outer surface and an inner surface, wherein the inner surface comprises a cotton textile having a water-resistant coating, wherein the water-resistant coating comprises a thermoplastic polyurethane, TPU, membrane. A method of manufacture is also provided comprising obtaining a cotton textile, bonding a water-resistant membrane to a surface of the cotton textile, wherein the water-resistant membrane comprises thermoplastic polyurethane, TUP, and polyethylene terephthalate, PET; and manufacturing a bag using the water-resistant material, wherein the bag comprises an inner surface, and wherein the water-resistant layer is arranged on the inner surface of the bag.

Abstract: A circuit includes a microcontroller having a first terminal and a second terminal. The microcontroller is configured to: receive a signal associated with operation of a power converter at the first terminal; adjust a switch control signal at the second terminal responsive to the signal; measure a frequency of the switch control signal; compare the measured frequency responsive to at least one envelope of a set of envelopes to obtain monitoring results; and perform control operations responsive to the monitoring results.

Abstract: An example apparatus includes: bandwidth estimator circuitry configured to: obtain a first memory transaction; and determine a consumed bandwidth associated with the memory transaction; and gate circuitry configured to: permit transmission of the memory transaction to a memory controller circuitry; determine whether to gate a second memory transaction generated by a source of the first memory transaction based on the consumed bandwidth of the first memory transaction; and when it is determined to gate the second memory transaction, prevent transmission of the second memory transaction for an amount of time based on the consumed bandwidth.

Abstract: A data storage interface layer provides access management and transformation of data stored in various backend storage clusters. The data storage interface can serve as a point of access for data accessors to access stored data via a consistent data access protocol, even when a data storage cluster on which requested data is stored may use a different protocol. The data storage interface can also provide in-line transformation of requested data and/or control of access to requested data.