Abstract: Disclosed are techniques for employing deep learning to analyze radar signals. In an aspect, an on-board computer of a host vehicle receives, from a radar sensor of the vehicle, a plurality of radar frames, executes a neural network on a subset of the plurality of radar frames, and detects one or more objects in the subset of the plurality of radar frames based on execution of the neural network on the subset of the plurality of radar frames. Further, techniques for transforming polar coordinates to Cartesian coordinates in a neural network are disclosed. In an aspect, a neural network receives a plurality of radar frames in polar coordinate space, a polar-to-Cartesian transformation layer of the neural network transforms the plurality of radar frames to Cartesian coordinate space, and the neural network outputs the plurality of radar frames in the Cartesian coordinate space.

Abstract: The invention provides anti-Jagged2 antibodies and methods of using the same.

Abstract: The present invention provides anti-HtrA1 antibodies (including bispecific anti-HtrA1 anti-Factor D antibodies) and methods of making and using the same, for example, in methods of treating HtrA1-associated disorders, ocular disorders, and/or complement-associated disorders.

Abstract: The present invention provides, among other aspects, functionalized chromophoric polymer dots comprising a hydrophobic core and a hydrophilic cap, and bioconjugates thereof. Also provided are improved methods for preparing functionalized chromophoric polymer dots. Methods for in vivo imaging and molecular labeling are also disclosed.

Abstract: Provided herein are methods and systems for analyzing a sample of a subject to determine whether the subject has, or is at risk of having or developing, a cancer, such as lung cancer.

Abstract: The invention relates to methods, compounds, compositions and vehicles for delivering 3-amino-1-propanesulfonic acid (3APS) in a subject, preferably a human subject. The invention encompasses compounds that will yield or generate 3APS, either in vitro or in vivo. Preferred compounds include amino acid prodrugs of 3APS for use, including but not limited to, the prevention and treatment of Alzheimer's disease.

Abstract: Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.

Abstract: An example apparatus includes: bandwidth estimator circuitry configured to: obtain a first memory transaction; and determine a consumed bandwidth associated with the memory transaction; and gate circuitry configured to: permit transmission of the memory transaction to a memory controller circuitry; determine whether to gate a second memory transaction generated by a source of the first memory transaction based on the consumed bandwidth of the first memory transaction; and when it is determined to gate the second memory transaction, prevent transmission of the second memory transaction for an amount of time based on the consumed bandwidth.

Abstract: Methods, systems, apparatus, and tangible non-transitory carrier media encoded with one or more computer programs for classifying an item. In accordance with particular embodiments, a labeling task is issued to workers participating in a crowdsourcing system. The labeling task includes evaluating an inferred classification that includes one or more of the class labels in a hierarchical classification taxonomy based at least in part on a description of the item and the class labels in the classification. Evaluation decisions are received from the crowdsourcing system. The classification is validated based on the evaluation decisions to obtain a validation result. The validating includes applying at least one consensus criterion to an aggregation of the received evaluation decisions. Data corresponding to one or more of the class labels in the classification is routed to respective destinations based on the validation result.

Abstract: Methods, apparatus, and processor-readable storage media for artificial intelligence-based techniques for automated visual data searching using edge devices are provided herein. An example computer-implemented method includes obtaining visual data from one or more edge devices; generating at least one automated searching tool by processing at least a portion of the obtained data using one or more artificial intelligence techniques; deploying the at least one automated searching tool to at least a portion of the one or more edge devices; and performing one or more automated actions based at least in part on data received, from at least a portion of the one or more edge devices, in connection with operation of the at least one automated searching tool.

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

Abstract: A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.

Abstract: The disclosure is direct to a unique system for delivering NMES and/or TENS therapy to one or more portions of a biological structure. In some embodiments, the biological structure includes a limb such as an elbow or knee. In some embodiments, the system includes a flexible panel with an integrated flexible circuit. In some embodiments, the flexible panel is configured to couple to and bend with a garment. In some embodiments, the flexible panel enables the coupling of one or more electrodes. In some embodiments, the flexible panel is removable from the garment which allows for the garment to be washed without exposing flexible panel electrical connections to submersion in a fluid.

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

Abstract: Disclosed herein is an optical filter configured for wavelength division and multiplexing capable of transmitting and receiving signals. The optical filter includes an optical waveguide configured to receive at an input multiple signals with different wavelengths. The optical filter includes a plurality of channels coupled at different locations along a length of the optical waveguide. Each of the plurality of channels is configured to transmit a respective one of the multiple signals. A number of ring filter stages in a first channel of the plurality of channels that is closer to the input of the optical waveguide is greater than a second channel in the plurality of channels further away from the input of the optical waveguide.

Abstract: A transmission mechanism includes a chain. The chain includes a plurality of inner link units and a plurality of outer link units. Each of the inner link units includes two inner chain plates. Each of the inner chain plates has an inner waist section. At least one of the outer link units includes two outer chain plates. Each of the outer chain plates has an outer waist section that has a protruding part and a recessed part. A distance between the inner waist sections of each of the inner link units is smaller than a distance between the protruding parts of the outer chain plates of the at least one of the outer link units, and is equal to or smaller than a distance between the recessed parts of the at least one of the outer link units.

Abstract: In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.

Abstract: A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.

Abstract: In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.