Abstract: A chain plate includes two end segments, and an intermediate segment between the end segments. One of the end segments has an extension portion extending away from a rod hole of the end segment in a lengthwise direction. A distance from a center of the rod hole to an edge of the end segment in the lengthwise direction is greater than a distance from the center of the rod hole to an edge of the end segment in a widthwise direction. An inner surface of the chain plate has a first inclined region corresponding to a peripheral region of the end segment, and a second inclined region corresponding to the extension portion and between the first inclined region and the rod hole. The intermediate segment is formed with a recess.

Abstract: A data storage interface provides access to data storage clusters that may not otherwise be accessible to data accessors. The data storage interface can serve as a point of access for data accessors to access stored data via a consistent data access protocol, even when a data storage cluster on which requested data is stored may use a different protocol. The data storage interface can also provide access across network boundaries, such as those between different private cloud computing systems (e.g., virtual private clouds or “VPCs”).

Abstract: A device includes a data path, a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address, and a controller connected to the data path and configured to receive the request to write the data value to the memory address and to calculate a Hamming code of the data value. The controller is configured to transmit the data value and the Hamming code on the data path. The device includes an external memory interleave connected to the data path. The external memory interleave is configured to receive the data value and calculate a test Hamming code of the data value and to determine whether to send the data value to an external memory interface to be written to the memory address based on a comparison of the Hamming code and the test Hamming code.

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.

Abstract: Certain aspects of the present disclosure provide techniques for providing automated intelligence in a support session. In one example, a method includes generating a set of tokens based on a text-based query posted by a support agent to a live chat thread; generating a set of vectors based on the set of tokens; extracting a set of features based on the set of tokens; generating a query vector based on the set of vectors and the set of features; determining a predicted intent of the text-based query based on the query vector, wherein the predicted intent is one of a plurality of predefined intents; determining a predicted answer to the text-based query based on: the query vector; and the predicted intent; and providing the predicted answer to the text-based query in the live chat thread.

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache preload operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

Abstract: A device includes a data path, a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address, and a controller connected to the data path and configured to receive the request to write the data value to the memory address and to calculate a Hamming code of the data value. The controller is configured to transmit the data value and the Hamming code on the data path. The device includes an external memory interleave connected to the data path. The external memory interleave is configured to receive the data value and calculate a test Hamming code of the data value and to determine whether to send the data value to an external memory interface to be written to the memory address based on a comparison of the Hamming code and the test Hamming code.

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache preload operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

Abstract: A transmission mechanism includes a chain. The chain includes a plurality of inner link units and a plurality of outer link units. Each of the inner link units includes two inner chain plates. Each of the inner chain plates has an inner waist section. At least one of the outer link units includes two outer chain plates. Each of the outer chain plates has an outer waist section that has a protruding part and a recessed part. A distance between the inner waist sections of each of the inner link units is smaller than a distance between the protruding parts of the outer chain plates of the at least one of the outer link units, and is equal to or smaller than a distance between the recessed parts of the at least one of the outer link units.

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

Abstract: Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.

Abstract: A chain tensioning device is adapted to be coupled to a vehicle body and to be adjacent to a chain, and includes a connecting segment, a metallic resilient segment, a fixing member and a guiding member. The connecting segment includes a securing portion adapted to be coupled to the vehicle body and an extending portion adapted to be under the chain. The resilient segment is connected to the extending portion of the connecting segment via the fixing member, and has a spring constant which ranges from 0.01 to 1000 N/mm, and a Young's modulus which ranges from 69 to 220 megapascals. The guiding member is connected to the resilient segment and is biased by the resilient segment for maintaining a tension of the chain.

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

Abstract: Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

Abstract: Disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. All of the data elements hare the same data size, which is specified by one or more coding bits. The data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. The register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.

Abstract: A chain plate includes two end segments, and an intermediate segment between the end segments. One of the end segments has an extension portion extending away from a rod hole of the end segment in a lengthwise direction. A distance from a center of the rod hole to an edge of the end segment in the lengthwise direction is greater than a distance from the center of the rod hole to an edge of the end segment in a widthwise direction. An inner surface of the chain plate has a first inclined region corresponding to a peripheral region of the end segment, and a second inclined region corresponding to the extension portion and between the first inclined region and the rod hole. The intermediate segment is formed with a recess.

Abstract: Disclosed embodiments include a data processing apparatus having a processing core, a memory, and a streaming engine. The streaming engine is configured to receive a plurality of data elements stored in the memory and to provide the plurality of data elements as a data stream to the processing core, and includes an address generator to generate addresses corresponding to locations in the memory, a buffer to store the data elements received from the locations in the memory corresponding to the generated addresses, and an output to supply the data elements received from the memory to the processing core as the data stream.