POWER SWITCH PACKAGING WITH PRE-FORMED ELECTRICAL CONNECTIONS FOR CONNECTING INDUCTOR TO ONE OR MORE TRANSISTORS
In some examples, device includes an integrated circuit (IC) inside a first insulating layer, an inductor, and a second insulating layer arranged between the first insulating layer and the inductor. The first insulating layer shares an interface with the second insulating layer, and the inductor is attached to the second insulating layer. The device further includes a conductive path configured to conduct electricity between the IC and the inductor, wherein the conductive path is inside the second insulating layer.
This disclosure relates to semiconductor packaging.
BACKGROUNDSurface-mount technology (SMT) is a production method for electronics that involves attaching components and devices on a printed circuit board (PCB). Components and devices may be soldered on the PCB to provide stability and electrical connections through the traces in the PCB.
SUMMARYIn some examples, this disclosure describes techniques for a device that includes an integrated circuit (IC) inside a first insulating layer, an inductor, and a second insulating layer arranged between the first insulating layer and the inductor. The first insulating layer shares an interface with the second insulating layer, and the inductor is attached to the second insulating layer. The device further includes a conductive path configured to conduct electricity between the IC and the inductor, wherein the conductive path is inside the second insulating layer.
In some examples, this disclosure describes a method including forming a second insulating layer, forming a conductive path inside the second insulating layer, and electrically connecting an IC to the conductive path, wherein the IC is outside of the second insulating layer. The method further includes forming a first insulating layer sharing an interface with the second insulating layer, wherein the IC is inside the first insulating layer, and electrically connecting an inductor to the conductive path in the second insulating layer.
In some examples, this disclosure describes a power converter that includes at least two transistors inside a first insulating layer, wherein each transistor of the at least two transistors includes a control terminal and at least two load terminals, a first load terminal of a first transistor is electrically coupled to an input node of the power converter, a second load terminal of a first transistor is electrically coupled to a switch node, and a first load terminal of a second transistor is electrically coupled to the switch node, a driver circuit configured to deliver signals to the control terminal of the first transistor and the control terminal of the second transistor. The power converter further includes an inductor electrically coupled to a conductive path and an output node of the power converter, and a second insulating layer arranged between the at least two transistors and the inductor, wherein the first insulating layer shares an interface with the second insulating layer. The power converter further includes the conductive path, wherein the conductive path is electrically coupled to the switch node, and the conductive path is inside the second insulating layer.
The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.
A power converter may include two or more transistors and an inductor. Constructing the power converter on a printed circuit board (PCB) may include attaching an integrated circuit (IC), which contains the two or more transistors, to the PCB and attaching the inductor, as a module separate from the IC, to the PCB. In this configuration, the IC and the inductor may communicate through electrical traces in the PCB.
To shorten the connection between the IC and the inductor, the inductor may be stacked on top of the IC on the PCB. The IC may be inside a first insulating layer that interfaces with a second insulating layer situated between the inductor and the first insulating layer. The connection, or “conductive path,” between the IC and the inductor may be inside the second insulating layer. By shortening the conductive path and isolating the conductive path from the PCB, the power converter may experience less noise and parasitic capacitance, as compared to attaching the IC and the inductor to the PCB as separate modules.
Power converter 2 may include device 4, which may include integrated circuit (IC) 6. Power converter 2 may include transistors 10A, 10B, inductor 16, capacitor 20, and pulse-width modulation (PWM) control and driver 12. In some examples, power converter 2 may contain more or fewer components than the components depicted in
Transistors 10A, 10B may comprise metal-oxide semiconductor (MOS) field-effect transistors (FETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), high-electron-mobility transistors (HEMTs), gallium-nitride (GaN) based transistors, and/or other elements that use voltage for control. Transistors 10A, 10B may comprise n-type transistors or p-type transistors, and transistors 10A, 10B may comprise vertical power transistors. For a vertical power transistor, the source terminal and the drain terminal may be on opposite sides or opposite surfaces of the transistor. Current in a vertical power transistor may flow through the transistor from top to bottom. In some examples, transistors 10A, 10B may comprise other analog devices such as diodes. Transistors 10A, 10B may also include freewheeling diodes connected in parallel with transistors to prevent reverse breakdown of transistors 10A, 10B. In some examples, transistors 10A, 10B may operate as switches or as analog devices. In still other examples, transistors 10 may include more than two transistors, such as in multi-phase power converters or other more complex power circuits. For example, in a multi-phase power converter, power converter 2 may have one high-side transistor and one low-side transistor for each phase. Therefore, a multi-phase power converter may include one or more replications of power converter 2 as depicted in
Transistors 10A, 10B may comprise various material compounds, such as silicon (Si), silicon carbide (SiC), Gallium Nitride (GaN), or any other combination of one or more semiconductor materials. To take advantage of higher power density requirements in some circuits, power converters may operate at higher frequencies. Improvements in magnetics and faster switching, such as Gallium Nitride (GaN) switches, may support higher frequency converters. These higher frequency circuits may require control signals to be sent with more precise timing than for lower frequency circuits.
PWM control and driver 12 may deliver signals and/or voltages to the control terminals of transistors 10A, 10B.
Inductor 16 may comprise a coil inductor that is outside of IC 6. Inductor 16 may connect to switch node 14 and output node 18. Inductor 16 may impede the flow of alternating-current (AC) electricity, while allowing DC electricity to flow between switch node 14 and output node 18.
Capacitor 20 may comprise a film capacitor, an electrolytic capacitor, a ceramic capacitor, or any other suitable type of capacitor or capacitors that is outside of IC 6 and device 4. Capacitor 20 may be an optional component in power converter 2. Capacitor 20 may connect to output node 18 and reference node 22. Capacitor 20 may impede the flow of DC electricity, while allowing AC electricity to flow between output node 18 and reference node 22. Capacitor 20 may act as a smoothing capacitor for the voltage at output node 18 to moderate fluctuations in the voltage at output node 18.
Together, studs 40 and metal layers 32 may comprise pre-formed electrically conductive paths through the insulating layer comprising molding compound 50. In some examples, the tops of studs 40A, 40B may be exposed after the formation of molding compound 50.
Metal layers 32, studs 40, and molding compound 50 may comprise a pre-fabricated layer. The conductive paths created by metal layers 32 and studs 40 may comprise pre-formed metal conductive paths or pillars. The conductive paths including metal layers 32 and studs 40 may in some cases have better current carrying characteristics than laser-drilled vias. Laser-drilled vias may have a conical shape with a smaller thickness at one end. Laser-drilled vias may perform worse at high switching speeds, as compared to pre-formed conductive paths. Pre-formed conductive paths may have more consistent size and shape, as compared to laser-drilled vias.
IC 70 may comprise a so-called “flip chip” and may contain two or more transistors that are configured to conduct electricity with conductive pad 72 and connectors 74A, 74B. The transistors in IC 70 may experience voltages from less than one volt up to two thousand volts and currents from less than one milliampere up to hundreds of amperes. IC 70 may contain a circuit that is similar to IC 4 in
Inductor 92 may include leads 94A, 94B which may conduct electricity and support inductor 92. Leads 94A, 94B may attach to respective studs 40A, 40B by respective connectors 96A, 96B. Connectors 96A, 96B may comprise solder, electrically conductive paste or adhesive, or any other suitable material for securing leads 94A, 94B to respective studs 40A, 40B.
In accordance with the techniques of this disclosure, device 90 may comprise IC 70 inside a first insulating layer that includes molding compound 80. Device 90 may further comprise a second insulating layer that includes molding compound 50 arranged between the first insulating layer and inductor 92. The first insulating layer, which includes molding compound 80, may share an interface with the second insulating layer, to which inductor 92 may attach. Device 90 may further comprise a conductive path including metal layer 32A and stud 40A. The conductive path may be configured to conduct electricity between IC 70 and inductor 92 inside the second insulating layer that includes molding compound 50.
The conductive path may conduct electricity between IC 70 and inductor 92 through connector 74A, connector 96A, and lead 94A. The conductive path may include a metal pillar, such as a copper pillar, in the form of stud 40A through molding compound 50. Together, connector 74A, metal layer 32A, stud 40A, connector 96A, and lead 94A may comprise, or be electrically connected to, switch node 14 in
Device 90 may be mounted on a PCB (not shown in
In some examples, IC 70 may comprise two or more transistors, each transistor with two load terminals and one gate terminal. One or more of the transistors may comprise a vertical transistor with a first load terminal connected to a top side of IC 70, such as connector 74A or 74B, and a second load terminal connected to a bottom side of IC 70, such as conductive pad 72. One or more of the transistors may comprise a lateral transistor with both load terminals connected to the same side of IC 70. IC 70 may also have electrical connections to reference voltage and an input node. As shown in
Lead 104A may conduct electricity between inductor 102 and metal layer 106A, which may conduct electricity with IC 108A. Metal layer 106A may connect to connections 110A-110C on IC 108A. Metal layer 106A may be similar to switch node 14 and/or metal layer 32A in
Lead 104B may conduct electricity between inductor 102 and metal layer 106B, which may conduct electricity with pad 108B. Pad 108B may conduct electricity with the bottom of device 100, which may be attached to a PCB. Lead 104B, metal layer 106B, and pad 108B may be similar in operation to output node 18 in
Metal layers 106C-106G may conduct electricity with connections 110D-110K on IC 108A. One or more of connections 110D-110K may correspond to reference node 22 in
IC 108A may include vertical transistors or lateral transistors. Vertical transistors may conduct current between the top and bottom of IC 108A. As shown in
Connections 110 are depicted in
Insulator 112 is depicted as a single layer but may comprise two or more layers, as shown in
Metal layers 106E-106G may connect to other components or nodes into or out of the page in
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The following numbered examples demonstrate one or more aspects of the disclosure.
Example 1A device includes an IC inside a first insulating layer, an inductor, and a second insulating layer arranged between the first insulating layer and the inductor. The first insulating layer shares an interface with the second insulating layer, and the inductor is attached to the second insulating layer. The device further includes a conductive path configured to conduct electricity between the IC and the inductor, wherein the conductive path is inside the second insulating layer.
Example 2The device of example 1, wherein the IC comprises at least two transistors, an electrical connection to a reference voltage, an electrical connection to an input node, and an electrical connection to the conductive path.
Example 3The device of any combination of examples 1-2, wherein each transistor of the at least two transistors includes a control terminal and two load terminals. One transistor of the at least two transistors is a vertical transistor that includes at least one load terminal that is electrically connected to a top side of the IC and at least one load terminal that is electrically connected to a bottom side of the IC.
Example 4The device of any combination of examples 1-3, wherein each transistor of the at least two transistors comprises a lateral transistor that includes at least two load terminals that are electrically connected to a top side of the IC or a bottom side of the IC.
Example 5The device of any combination of examples 1-4, wherein the IC comprises a driver circuit configured to deliver signals to the control terminal of each transistor of the at least two transistors.
Example 6The device of any combination of examples 1-5, wherein the first transistor comprises an n-type field effect transistor (FET), and the second transistor comprises an n-type FET. A first load terminal of a first transistor of the at least two transistors is coupled to the input node, and a second load terminal of the first transistor is coupled to the conductive path and to a first load terminal of a second transistor of the at least two transistors. A second load terminal of the second transistor is coupled to the reference voltage.
Example 7The device of any combination of examples 1-6, wherein the first insulating layer comprises an encapsulating material surrounding the IC, and the conductive path does not extend into the encapsulating material.
Example 8The device of any combination of examples 1-7, wherein the conductive path is coupled to the IC by a solder ball, electrically conductive paste, or a copper pillar.
Example 9The device of any combination of examples 1-8, wherein the IC, the conductive path, and the inductor comprise a power converter.
Example 10The device of any combination of examples 1-9, wherein the conductive path comprises a pre-formed copper pillar through the second insulating layer; and the conductive path does not extend into the first insulating layer.
Example 11A method includes forming a second insulating layer, forming a conductive path inside the second insulating layer, and electrically connecting an IC to the conductive path, wherein the IC is outside of the second insulating layer. The method further includes forming a first insulating layer sharing an interface with the second insulating layer, wherein the IC is inside the first insulating layer, and electrically connecting an inductor to the conductive path in the second insulating layer.
Example 12The method of example 11, further comprising electrically connecting the IC to a reference voltage and electrically connecting the IC to an input node, wherein the IC comprises at least two transistors.
Example 13The method of any combination of examples 11-12, wherein each transistor of the at least two transistors includes a control terminal and two load terminals. One transistor of the at least two transistors comprises a vertical transistor, wherein the vertical transistor includes at least one load terminal that is electrically connected to a top side of the IC and at least one load terminal that is electrically connected to a bottom side of the IC.
Example 14The method of any combination of examples 11-13, wherein each transistor of the at least two transistors comprises a lateral transistor, and each transistor of the at least two transistors includes at least two load terminals that are electrically connected to a top side of the IC or a bottom side of the IC.
Example 15The method of any combination of examples 11-14, wherein the first transistor comprises an n-type FET, and the second transistor comprises an n-type FET. A first load terminal of a first transistor of the at least two transistors is coupled to the input node, a second load terminal of the first transistor is coupled to the conductive path and to a first load terminal of a second transistor of the at least two transistors, and a second load terminal of the second transistor is coupled to the reference voltage.
Example 16The method of any combination of examples 11-15, wherein electrically connecting the IC to the conductive path comprises: depositing solder on a conductive bump on the interface; and attaching the IC to the solder by melting the solder.
Example 17The method of any combination of examples 11-16, wherein forming the conductive path occurs before forming the conductive path inside the second insulating layer. The method further includes forming a second metal pillar before forming the second insulating layer, wherein the second metal pillar is inside the second insulating layer, and flipping the second insulating layer before electrically connecting the IC to the conductive path. The method further includes forming a first metal pillar before forming the first insulating layer, wherein the first metal pillar is inside the first insulating layer, and grinding down the first insulating layer to expose the first metal pillar before electrically connecting the inductor to the conductive path in the second insulating layer.
Example 18A power converter includes at least two transistors inside a first insulating layer, wherein each transistor of the at least two transistors includes a control terminal and at least two load terminals, a first load terminal of a first transistor is electrically coupled to an input node of the power converter, a second load terminal of a first transistor is electrically coupled to a switch node, and a first load terminal of a second transistor is electrically coupled to the switch node, a driver circuit configured to deliver signals to the control terminal of the first transistor and the control terminal of the second transistor. The power converter further includes an inductor electrically coupled to a conductive path and an output node of the power converter, and a second insulating layer arranged between the at least two transistors and the inductor, wherein the first insulating layer shares an interface with the second insulating layer. The power converter further includes the conductive path, wherein the conductive path is electrically coupled to the switch node, and the conductive path is inside the second insulating layer.
Example 19The power converter of example 19, wherein the first transistor comprises a vertical n-type FET, and the second transistor comprises a vertical n-type FET.
Example 20The power converter of any combination of examples 19-20, further comprising an encapsulating material surrounding the at least two transistors, wherein the conductive path does not extend into the encapsulating material.
Various examples of the disclosure have been described. Any combination of the described systems, operations, or functions is contemplated. These and other examples are within the scope of the following claims.
Claims
1: A device comprising:
- a conductive path;
- an integrated circuit (IC) inside a first insulating layer, wherein the IC includes: a first electrical connection to a reference voltage, a second electrical connection to an input node, and a third electrical connection to the conductive path;
- an inductor;
- a second insulating layer arranged between the first insulating layer and the inductor, wherein: the first insulating layer shares an interface with the second insulating layer, the inductor is attached to the second insulating layer, the conductive path is configured to conduct electricity between the IC and the inductor, and the conductive path is inside the second insulating layer.
2: The device of claim 1, wherein the IC comprises at least two transistors.
3: The device of claim 2, wherein:
- each transistor of the at least two transistors includes a control terminal and two load terminals; and
- one transistor of the at least two transistors comprises a vertical transistor, wherein the vertical transistor includes at least one load terminal that is electrically connected to a top side of the IC and at least one load terminal that is electrically connected to a bottom side of the IC.
4: The device of claim 2, wherein:
- each transistor of the at least two transistors comprises a lateral transistor; and
- each transistor of the at least two transistors includes at least two load terminals that are electrically connected to a top side of the IC or a bottom side of the IC.
5: The device of claim 2, wherein the IC comprises a driver circuit configured to deliver signals to the control terminal of each transistor of the at least two transistors.
6: The device of claim 3, wherein:
- the first transistor comprises an n-type field effect transistor (FET);
- the second transistor comprises an n-type FET;
- a first load terminal of a first transistor of the at least two transistors is coupled to the input node;
- a second load terminal of the first transistor is coupled to the conductive path and to a first load terminal of a second transistor of the at least two transistors; and
- a second load terminal of the second transistor is coupled to the reference voltage.
7: The device of claim 1, wherein the first insulating layer comprises an encapsulating material surrounding the IC, wherein the conductive path does not extend into the encapsulating material.
8: The device of claim 1, wherein the conductive path is coupled to the IC by a solder ball, electrically conductive paste, or a copper pillar.
9: The device of claim 1, wherein the IC, the conductive path, and the inductor comprise a power converter.
10: The device of claim 1, wherein:
- the conductive path comprises a pre-formed copper pillar through the second insulating layer; and
- the conductive path does not extend into the first insulating layer.
11: A method comprising:
- forming a second insulating layer;
- forming a conductive path inside the second insulating layer;
- electrically connecting an integrated circuit (IC) to the conductive path, wherein the IC is outside of the second insulating layer;
- forming a first insulating layer sharing an interface with the second insulating layer, wherein the IC is inside the first insulating layer;
- electrically connecting an inductor to the conductive path in the second insulating layer;
- electrically connecting the IC to a reference voltage; and
- electrically connecting the IC to an input node.
12. (canceled)
13: The method of claim 11, wherein:
- each transistor of the at least two transistors includes a control terminal and two load terminals;
- one transistor of the at least two transistors comprises a vertical transistor, wherein the vertical transistor includes at least one load terminal that is electrically connected to a top side of the IC and at least one load terminal that is electrically connected to a bottom side of the IC.
14: The method of claim 11, wherein:
- each transistor of the at least two transistors comprises a lateral transistor; and
- each transistor of the at least two transistors includes at least two load terminals that are electrically connected to a top side of the IC or a bottom side of the IC.
15: The method of claim 13, wherein:
- the first transistor comprises an n-type field effect transistor (FET);
- the second transistor comprises an n-type FET;
- a first load terminal of a first transistor of the at least two transistors is coupled to the input node;
- a second load terminal of the first transistor is coupled to the conductive path and to a first load terminal of a second transistor of the at least two transistors; and
- a second load terminal of the second transistor is coupled to the reference voltage.
16: The method of claim 11, wherein electrically connecting the IC to the conductive path comprises:
- depositing solder on a conductive bump on the interface; and
- attaching the IC to the solder by melting the solder.
17: The method of claim 11, wherein forming the conductive path occurs before forming the conductive path inside the second insulating layer, the method further comprising:
- forming a second metal pillar before forming the second insulating layer, wherein the second metal pillar is inside the second insulating layer;
- flipping the second insulating layer before electrically connecting the IC to the conductive path;
- forming a first metal pillar before forming the first insulating layer, wherein the first metal pillar is inside the first insulating layer; and
- grinding down the first insulating layer to expose the first metal pillar before electrically connecting the inductor to the conductive path in the second insulating layer.
18: A power converter comprising:
- at least two transistors inside a first insulating layer, wherein: each transistor of the at least two transistors includes a control terminal and at least two load terminals, a first load terminal of a first transistor is electrically coupled to an input node of the power converter, a second load terminal of a first transistor is electrically coupled to a switch node, and a first load terminal of a second transistor is electrically coupled to the switch node,
- a driver circuit configured to deliver signals to the control terminal of the first transistor and the control terminal of the second transistor;
- an inductor electrically coupled to a conductive path and an output node of the power converter;
- a second insulating layer arranged between the at least two transistors and the inductor, wherein the first insulating layer shares an interface with the second insulating layer; and
- the conductive path, wherein: the conductive path is electrically coupled to the switch node, and the conductive path is inside the second insulating layer.
19: The power converter of claim 18, wherein:
- the first transistor comprises a vertical n-type field-effect transistor (FET); and
- the second transistor comprises a vertical n-type FET.
20: The power converter of claim 18, further comprising an encapsulating material surrounding the at least two transistors, wherein the conductive path does not extend into the encapsulating material.
21: The power converter of claim 18, wherein:
- the conductive path comprises a pre-formed copper pillar through the second insulating layer; and
- the conductive path does not extend into the first insulating layer.
Type: Application
Filed: Aug 19, 2016
Publication Date: Feb 22, 2018
Inventors: Eung San Cho (Torrance, CA), Danny Clavette (Greene, RI)
Application Number: 15/241,981