Abstract: A neurostimulation (NS) system and method are provided. The NS system includes an array of electrodes positioned within a patient. The array of electrodes includes an active electrode. The active electrode is configured to be a cathode electrode located proximate to neural tissue of interest that is associated with a target region. The NS system includes an anode electrode and an electromagnetic interference (EMI) antenna. A control circuit is configured to control delivery of a NS therapy during a therapy delivery interval. The NS therapy is to be delivered between the anode electrode and the active electrode. The NS system develops a residual voltage between the anode electrode and the active electrode over the therapy delivery interval. A current regulator (CR) circuit is connected to the cathode electrode. The CR circuit is configured to control current flow through the cathode electrodes.

Abstract: A neurostimulation system (NS) includes an array of electrodes positioned within a patient with an active cathode electrode located proximate to target neural tissue. A control circuit is controls delivery of therapy during a therapy delivery interval, with the therapy being delivered between an anode electrode and the active electrode. A current regulator circuit (CRC) is connected to the cathode electrode and controls current flow through the cathode electrodes. The control circuit manages the CRC to control a discharge current flow over the discharge operation to discharge developed residual voltage between the anode electrode and the active electrode in a manner that follows an actively emulated passive discharge (AEPD) profile. During the discharge operation, the CRC is connected to the inactive electrode, and receives, as a first input, an EMI feedback signal.

Abstract: An implantable medical device (IMD) includes an adjustable capacitive voltage multiplier (CVM) that is responsive to diagnostic circuitry configured to provide control signals within a single stimulation current pulse for adjusting the voltage output applied to an electrode of the IMD's lead system. A control counter is coupled to the diagnostic circuitry for incrementing or decrementing an N-bit counter output signal operative to reconfigure a charge pump arrangement of the CVM so as to facilitate an adjusted voltage output.

Abstract: A neurostimulation system (NS) includes an array of electrodes positioned within a patient with an active cathode electrode located proximate to target neural tissue. A control circuit is controls delivery of therapy during a therapy delivery interval, with the therapy being delivered between an anode electrode and the active electrode. A current regulator circuit (CRC) is connected to the cathode electrode and controls current flow through the cathode electrodes. The control circuit manages the CRC to control a discharge current flow over the discharge operation to discharge developed residual voltage between the anode electrode and the active electrode in a manner that follows an actively emulated passive discharge (AEPD) profile. During the discharge operation, the CRC is connected to the inactive electrode, and receives, as a first input, an EMI feedback signal.

Abstract: A neurostimulation (NS) system and method are provided. The system includes a power supply having positive and negative terminals. The negative terminal defines a reference ground. An array of electrodes are positioned within a patient. The array of electrodes includes first and second active electrodes for delivering stimulation therapy configured to be located proximate to neural tissue of interest that is associated with a target region. A control circuit is configured to control delivery of stimulation current for a NS therapy between the first and second electrodes. A current regulator (CR) circuit is connected to, and configured to control current flow through, at least the first electrode during delivery of the stimulation therapy under direction of the control circuit. A floating power supply is connected across power supply terminals of the CR circuit. The CR circuit and floating power supply are coupled to a floating ground node that is electrically separate from the reference ground.

Abstract: The present disclosure provides systems and methods for an output architecture for an implantable pulse generator of a neurostimulation system. The output architecture includes a power supply, a plurality of outputs, a global source current regulator coupled to the power supply and operable to source current from the power supply to the plurality of outputs through a plurality of source current branches, a global sink current regulator operable to sink current from the plurality of outputs to ground through a plurality of sink current branches, a current source branch selector operable to select, for each of the plurality of outputs, an amount of current sourced from the plurality of source current branches, and a current sink branch selector operable to select, for each of the plurality of outputs, an amount of current sunk to the plurality of sink current branches.

Abstract: In one embodiment, an implantable pulse generator (IPG) for providing a neurostimulation therapy, comprises: pulse generation circuitry and pulse delivery circuitry for controlling generation and delivery of electrical pulses to a patient using one or more electrodes of a stimulation lead; measurement circuitry for determining characteristics of one or more electrodes selected for delivery of electrical pulses; and a processor for controlling the IPG according to executable code; wherein the IPG is adapted to calculate values for an impedance model of the one or more selected electrodes using the determined plurality of voltage measurements and to adjust current levels for the exponentially decreasing current pattern based on the calculated values for the impedance mode.

Abstract: Embodiments are directed to an implantable medical device comprising stimulation circuitry for controlling delivery of a medical therapy to a patient, a processor for controlling the IMD according to executable code, and a power source. The implantable medical device may further include current regulator circuitry comprising electrode selection circuitry that is configured to select electrodes for use during a discharge mode, and a programmable current regulator configured to provide an exponentially decreasing discharge current to the selected electrodes from the power source. A current output of a programmable current regulator may be decreased in precalculated steps to create the exponentially decreasing discharge current applied to the selected electrodes.

Abstract: In one embodiment, an implantable medical device (MD), comprises: a processor for controlling the IMD; circuitry for providing therapeutic or diagnostic medical operations for a patient; wireless communication circuitry for conducting wireless communications; a non-rechargeable battery; and device power control circuitry comprising; at least one capacitor; charging control circuitry for switching between charging the at least one capacitor using the non-rechargeable battery and discharging the at least one capacitor to provide power for device operations; wherein the IMD is configured to maintain a count related to a number of times of discharge of the at least one capacitor to provide an end-of-life estimation for the IMD.

Abstract: Embodiments are directed to an implantable medical device comprising therapeutic stimulation circuitry for controlling delivery of a medical therapy to a patient, the therapeutic stimulation circuitry having at least one lead having electrodes for delivering the medical therapy. The implantable medical device further comprises measurement circuitry for determining characteristics of the at least one lead, a processor for controlling the IMD according to executable code, and memory for storing data and executable code, wherein the executable code comprises instructions for causing the processor to receive a plurality of voltage measurements associated with the electrodes, and calculate values for an impedance model of the electrode/tissue interface.

Abstract: A Kelvin connection scheme, apparatus and method for effectuating residual voltage measurements with respect to one or more electrodes of a lead system associated with an implantable medical device (IMD). In one example implementation, terminals of at least one DC blocking stimulation capacitor or at least one AC-coupling sense capacitor associated with at least one inactive electrode of the lead system are used as one Kelvin connection terminal of a measurement circuit path whereas a counter Kelvin connection terminal with respect to a selection of at least one active electrode is effectuated across the electrode/tissue interface using either at least one DC blocking stimulation capacitor or at least one AC-coupling sense capacitor provided therewith.

Abstract: An apparatus and method for providing split stimulation currents in a pulse generator. In one embodiment, a current regulator of the pulse generator includes a digitally-programmable analog voltage generator coupled to a first input of an error amplifier that receives a second input controlled by a programmable resistor network configured to control a programmable total stimulation current output. A plurality of current splitting switches are operative to split the programmable total stimulation current output into a corresponding plurality of split current segments, which may be individually mapped to a selected set of lead electrodes across one or more implantable leads associated with the pulse generator.

Abstract: A low standby current power-on reset circuit is described. A first NMOS transistor's drain is coupled to a first PMOS transistor's drain; source coupled to ground line; and gate coupled to a first capacitor coupled to ground line. The first PMOS transistor's source is coupled to power line; gate coupled to second capacitor coupled to ground line; and drain provides a power-on reset indication. A second PMOS transistor's source is coupled to power line; drain is coupled to drain of second NMOS transistor, gates of first PMOS, second PMOS, and second NMOS transistors, and second capacitor. The second NMOS transistor's source is coupled to gate of first NMOS transistor and first capacitor. A discharge circuit is coupled to power line, ground line, and first and second capacitors for discharging the capacitors when a voltage on power line drops below a level determined by the second PMOS transistor's threshold voltage.

Abstract: An OTP bit cell includes a latch circuit of cross-coupled inverters. A floating gate PMOS transistor is inserted in each of the inverters. One or the other of the floating gate PMOS transistors is programmed through an included programming circuit so that a differential output of the latch circuit provides a corresponding logic state that is the same each time when read. To program a selected floating gate PMOS transistor, appropriate write inputs are applied to the programming circuit while a high reference voltage to the OTP bit cell is raised to a level such that the selected floating gate PMOS transistor is programmed.

Abstract: A low standby current power-on reset circuit is described. A first NMOS transistor's drain is coupled to a first PMOS transistor's drain; source coupled to ground line; and gate coupled to a first capacitor coupled to ground line. The first PMOS transistor's source is coupled to power line; gate coupled to second capacitor coupled to ground line; and drain provides a power-on reset indication. A second PMOS transistor's source is coupled to power line; drain is coupled to drain of second NMOS transistor, gates of first PMOS, second PMOS, and second NMOS transistors, and second capacitor. The second NMOS transistor's source is coupled to gate of first NMOS transistor and first capacitor. A discharge circuit is coupled to power line, ground line, and first and second capacitors for discharging the capacitors when a voltage on power line drops below a level determined by the second PMOS transistor's threshold voltage.

Abstract: An OTP bit cell includes a latch circuit of cross-coupled inverters. A floating gate PMOS transistor is inserted in each of the inverters. One or the other of the floating gate PMOS transistors is programmed through an included programming circuit so that a differential output of the latch circuit provides a corresponding logic state that is the same each time when read. To program a selected floating gate PMOS transistor, appropriate write inputs are applied to the programming circuit while a high reference voltage to the OTP bit cell is raised to a level such that the selected floating gate PMOS transistor is programmed.