Patents by Inventor Darel N Emmot
Darel N Emmot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11855913Abstract: An example hierarchical switching device may include sub-switches that form a fully interconnected all-to-all network, wherein the sub-switches comprise external output ports, internal input ports and internal output ports to exchange packets with other sub-switches within the fully interconnected all-to-all network. The switching device may further include a deadlockable storage, a storage partition and a switch controller. The deadlockable storage space is exclusively assigned to an internal input port of the internal input ports of the sub-switch including the deadlockable storage. The storage partition is exclusively assigned to an external output port of the external output ports and exclusively assigned to the internal input port. The switch controller is to route a packet destined for an external output port of a sub-switch through the internal input port of the sub-switch to the deadlockable storage or if the packet corresponds to the external output port, to the storage partition.Type: GrantFiled: October 31, 2018Date of Patent: December 26, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Nicholas G. McDonald, Darel N. Emmot
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Patent number: 10938751Abstract: Examples relate to hierarchical switching devices comprising a plurality of sub-switches forming a fully interconnected all-to-all network. The sub-switches comprise internal input ports and internal output ports to exchange packets with other sub-switches within the fully interconnected all-to-all network. The internal input ports of the sub-switches have exclusive access to a queue partition for each external output port of the respective sub-switch. A switch controller receives a packet at a first sub-switch of the plurality of sub-switches that is to be routed to a particular external output port of a second sub-switch of the plurality of sub-switches. The switch controller routes the packet directly from the first sub-switch to the second sub-switch using an internal output port of the first sub-switch and a queue partition of the second sub-switch that is for the particular external output port of the second sub-switch.Type: GrantFiled: April 18, 2018Date of Patent: March 2, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Nicholas George McDonald, Darel N Emmot
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Patent number: 10693808Abstract: Example implementations relate to hybrid arbitration of requests for access to a shared pool of resources. An example implementation includes receiving a set of requests for access to the shared pool of resources. The requests may each be from any number of traffic classes. A traffic class may be selected according to turn-based arbitration logic. Additionally, a request from each traffic class of a subset of received requests may be selected. A request selected by the age-based arbitration logic and of the selected traffic class may be granted access to the shared pool of resources.Type: GrantFiled: January 30, 2018Date of Patent: June 23, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Nicholas George McDonald, Darel N. Emmot
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Publication number: 20200136995Abstract: An example hierarchical switching device may include sub-switches that form a fully interconnected all-to-all network, wherein the sub-switches comprise external output ports, internal input ports and internal output ports to exchange packets with other sub-switches within the fully interconnected all-to-all network. The switching device may further include a deadlockable storage, a storage partition and a switch controller. The deadlockable storage space is exclusively assigned to an internal input port of the internal input ports of the sub-switch including the deadlockable storage. The storage partition is exclusively assigned to an external output port of the external output ports and exclusively assigned to the internal input port. The switch controller is to route a packet destined for an external output port of a sub-switch through the internal input port of the sub-switch to the deadlockable storage or if the packet corresponds to the external output port, to the storage partition.Type: ApplicationFiled: October 31, 2018Publication date: April 30, 2020Inventors: Nicholas G. McDonald, Darel N. Emmot
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Patent number: 10491545Abstract: Examples relate to virtual channel routing in networks considering VC actions to be performed by the packets while routed through the network. A packet is received at an input port of a network device of a network and an output port and a VC action is determined from a routing table associated to the input port based on a packet's destination network device. A VC mask is determined from a Virtual Channel Action Table (VCAT), associated to the routing table, based on a packet's ingress VC and the VC action. A particular VC among the set of VCs defined in the VC mask is selected and the packet is routed to the destination network device using the output port and the particular VC.Type: GrantFiled: May 26, 2017Date of Patent: November 26, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Nicholas George McDonald, Gary Gostin, Darel N. Emmot, Gregg B. Lesartre, Al Davis, Derek Alan Sherlock
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Publication number: 20190327189Abstract: Examples relate to hierarchical switching devices comprising a plurality of sub-switches forming a fully interconnected all-to-all network. The sub-switches comprise internal input ports and internal output ports to exchange packets with other sub-switches within the fully interconnected all-to-all network. The internal input ports of the sub-switches have exclusive access to a queue partition for each external output port of the respective sub-switch. A switch controller receives a packet at a first sub-switch of the plurality of sub-switches that is to be routed to a particular external output port of a second sub-switch of the plurality of sub-switches. The switch controller routes the packet directly from the first sub-switch to the second sub-switch using an internal output port of the first sub-switch and a queue partition of the second sub-switch that is for the particular external output port of the second sub-switch.Type: ApplicationFiled: April 18, 2018Publication date: October 24, 2019Inventors: Nicholas George MCDONALD, Darel N. EMMOT
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Publication number: 20190238482Abstract: Example implementations relate to hybrid arbitration of requests for access to a shared pool of resources. An example implementation includes receiving a set of requests for access to the shared pool of resources. The requests may each be from any number of traffic classes. A traffic class may be selected according to turn-based arbitration logic. Additionally, a request from each traffic class of a subset of received requests may be selected. A request selected by the age-based arbitration logic and of the selected traffic class may be granted access to the shared pool of resources.Type: ApplicationFiled: January 30, 2018Publication date: August 1, 2019Inventors: Nicholas George McDonald, Darel N. Emmot
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Patent number: 10355978Abstract: Example implementations relate to calculating a time to live (TTL). An example implementation includes receiving a transaction request containing a first time to live (TTL) from a requester. A second TTL for a transaction response may be computed, and a transaction response containing the second TTL may be transmitted.Type: GrantFiled: June 19, 2017Date of Patent: July 16, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B. Lesartre, Derek Alan Sherlock, Gary Gostin, Nicholas George McDonald, Alan Davis, Darel N. Emmot, John Kim
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Publication number: 20180367444Abstract: Example implementations relate to calculating a time to live (TTL). An example implementation includes receiving a transaction request containing a first time to live (TTL) from a requester. A second TTL for a transaction response may be computed, and a transaction response containing the second TTL may be transmitted.Type: ApplicationFiled: June 19, 2017Publication date: December 20, 2018Inventors: Gregg B. Lesartre, Derek Alan Sherlock, Gary Gostin, Nicholas George McDonald, Alan Davis, Darel N. Emmot, John Kim
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Publication number: 20180343210Abstract: Examples relate to virtual channel routing in networks considering VC actions to be performed by the packets while routed through the network. A packet is received at an input port of a network device of a network and an output port and a VC action is determined from a routing table associated to the input port based on a packet's destination network device. A VC mask is determined from a Virtual Channel Action Table (VCAT), associated to the routing table, based on a packet's ingress VC and the VC action. A particular VC among the set of VCs defined in the VC mask is selected and the packet is routed to the destination network device using the output port and the particular VC.Type: ApplicationFiled: May 26, 2017Publication date: November 29, 2018Inventors: Nicholas George McDonald, Gary Gostin, Darel N. Emmot, Gregg B. Lesartre, Al Davis, Derek Alan Sherlock
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Patent number: 9870814Abstract: A detection circuit is provided for a particular group of memory cells in a memory device, where the detection circuit is to be updated in response to at least one access of data and at least one neighboring group of memory cells. The particular group of memory cells is refreshed in response to an indication from the detection circuit, where the indication indicates presence of potential disturbance of the particular group of memory cells.Type: GrantFiled: October 22, 2012Date of Patent: January 16, 2018Assignee: Hewlett Packard Enterprise Development LPInventor: Darel N. Emmot
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Publication number: 20150294711Abstract: An access of data in a memory device is sampled. In response to the sampled access of data, a refresh operation is performed in the memory device.Type: ApplicationFiled: October 22, 2012Publication date: October 15, 2015Inventors: Blaine D. Gaither, Darel N. Emmot, Lidia Warnes
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Patent number: 8051250Abstract: A system for pushing data, the system includes a source node that stores a coherent copy of a block of data. The system also includes a push engine configured to determine a next consumer of the block of data. The determination being made in the absence of the push engine detecting a request for the block of data from the next consumer. The push engine causes the source node to push the block of data to a memory associated with the next consumer to reduce latency of the next consumer accessing the block of data.Type: GrantFiled: March 14, 2007Date of Patent: November 1, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Blaine D Gaither, Darel N. Emmot, Judson E. Veazey, Benjamin D. Osecky
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Patent number: 7629979Abstract: A system and method communicate information from a single-threaded application over multiple I/O busses to a computing subsystem for processing. In accordance with one embodiment, a method is provided that partitions state-sequenced information for communication to a computer subsystem, communicates the partitioned information to the subsystem over a plurality of input/output busses, and separately processes the information received over each of the plurality of input/output busses, without first se-sequencing the information.Type: GrantFiled: August 20, 2003Date of Patent: December 8, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Darel N. Emmot, Byron A. Alcorn, Ronald D. Larson
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Patent number: 7506130Abstract: A fully mirrored memory system includes at least one split memory bus, with each portion of the split memory bus having active memory and mirror memory. Each portion of the memory bus transfers a portion of the data for a memory transaction. If a memory unit is determined to be defective, one portion of the memory bus may be inactivated for hot swapping of memory, and the system can continue to operate using an active portion of the memory bus.Type: GrantFiled: May 22, 2002Date of Patent: March 17, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Darel N. Emmot, Eric M. Rentschler
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Patent number: 7451254Abstract: A method for allocating buffer capacity includes determining at least one characteristic of a first input/output (I/O) device that is coupled to a memory device interface, the memory device interface being configured to enable data transfers between the I/O device and a memory device, and buffering data corresponding to the first I/O device in a first portion of a buffer of the memory device interface, a size of the first portion being responsive to the at least one characteristic of the first I/O device.Type: GrantFiled: July 31, 2003Date of Patent: November 11, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: James R. Peterson, Matthew B. Lovell, Darel N. Emmot
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Publication number: 20080229009Abstract: A system for pushing data, the system includes a source node that stores a coherent copy of a block of data. The system also includes a push engine configured to determine a next consumer of the block of data. The determination being made in the absence oft he push engine detecting a request for the block of data from the next consumer. The push engine causes the source node to push the block of data to a memory associated with the next consumer to reduce latency of the next consumer accessing the block of data.Type: ApplicationFiled: March 14, 2007Publication date: September 18, 2008Inventors: Blaine D. Gaither, Darel N. Emmot, Judson E. Veazey, Benjamin D. Osecky
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Patent number: 7350127Abstract: An error correction code method comprises examining a validator of one of a plurality of data in a data stream at a first processing stage and directing the one of the plurality of data through at least one subsequent processing stage to a corrected output if the validator indicates an error. The method also includes directing the one of the plurality of data to the corrected output if the validator does not indicate an error.Type: GrantFiled: December 12, 2003Date of Patent: March 25, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Darel N. Emmot, Asheesh Kashyap
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Patent number: 7176914Abstract: A system and method are provided for directing the flow of data and instructions into at least one functional unit. In one embodiment of a system of components defining a plurality of nodes, a queue network manager (QNM) forming a part of each node, is provided. In this embodiment, the QNM comprises an interface to a network that supports intercommunication among the plurality of nodes, an interface configured to pass messages with a functional unit within the node, a random access memory (RAM) configured to store at least one of a message and a programmable instruction, and logic configured to control an operational aspect of a functional unit based on contents of the programmable instruction.Type: GrantFiled: May 16, 2002Date of Patent: February 13, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventor: Darel N. Emmot
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Patent number: 7009614Abstract: A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.Type: GrantFiled: May 3, 2005Date of Patent: March 7, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Darel N Emmot, Byron A Alcorn