Abstract: A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

Abstract: A system is provided for storing pixel data associated with a predetermined pixel region. The system is configured to store pixel data in a predetermined block of memory along with a fill check bit indicative of whether or not values for each pixel within the pixel region are the same as a predetermined reference pixel. The system also provides for the generation of a stream of pixel data corresponding to a pixel region by outputting a value for a pixel within the region that is equal to the reference pixel when the fill check bit is set.

Abstract: The present invention is broadly directed to a system of components defining a plurality of nodes and a random access memory (RAM) connected to each node. The system comprises at least one producer functional unit configured to perform a predetermined processing function resulting in the creation of at least one producer message, a communication mechanism configured to manage and control communication of messages with other nodes, at least one pointer that is configurable to point to a storage location within the RAM, and a message logic configured to interpret content of the at least one producer message, the message logic further configured to associate the producer message with a subset of the at least one pointers based upon the content of the at least one producer message, the message logic further configured to store the at least one producer message within the RAM at the locations indicated by the associated subset of at least one pointer.

Abstract: A system is provided for processing graphics data and outputting a stream of pixel data for display on an associated display device. The system is configured to store composed pixel data in a predetermined block of memory. The block of memory corresponds to a predetermined scan line of an associated display device.

Abstract: Methods and apparatus are provided for allocating correlated data sets, such as texture data, among first and second areas of memory in a computer graphics system. Each texture map in a series of texture maps is divided into a set of blocks of data. Each texture map that has a width greater than one block is divided into first and second map areas. Typically, the first and second map areas are the left and right halves of each texture map. Blocks of data from the first map areas of odd level texture maps are stored in the first memory area, blocks of data from the second map areas of even level texture maps are stored in the first memory area, blocks of data from the second map areas of odd level texture maps are stored in the second memory area and blocks of data from the first map areas of even level texture maps are stored in the second memory area. The blocks of data representing each texture map in the series of texture maps are stored in consecutive blocks of memory.

Abstract: The present invention is generally directed to a system and method for communicating information among components—e.g., from an originator node to a destination node, in a nodal computer architecture. In one embodiment, a method for communicating an information packet from an originator node to a destination node is provided. The method of this embodiment comprises splitting the information packet into a plurality of data segments, mapping the data segments to individual links extending between the originator node and the destination node, and reassembling the information packet at the destination node.

Abstract: A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

Abstract: A method and apparatus for controlling access to a multi-bank memory system. Multiple bank/row activation requests are presented by processes or systems seeking access to the memory. One of the banks of the memory is selected to be the target of a next bank/row activation request. Then, one of the requests corresponding to the chosen bank is selected and issued as the next request. Requests may be conditionally and iteratively selected until one is found whose target row corresponds to a currently active row in the target bank.

Abstract: Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be “tossed” and excluded from any batches currently under construction. The batch building process may then continue without the need for a batch flush responsive to the occurrence of the pixel collision. If the incoming pixel passes the depth comparison, then it may yet be possible to avoid flushing: The current rendering mode of the pipeline is determined. If the current rendering mode does not require read-modify-write operations, then the incoming pixel may be merged with the buffered pixel with which it collides. Merger of the two pixels may be accomplished by overwriting the buffered RGBA pixel components with those of the incoming pixel, but only those components corresponding to asserted bits in the incoming pixel's BEN.

Abstract: A data management system comprises a plurality of data transfer paths and a responder adapted to receive from an originator a data segment from each of a predetermined set of the data transfer paths. The system also comprises a context manager adapted to reassemble the data segments into a data communication based on the predetermined set of data transfer paths and a mapping order of the data segments.

Abstract: Methods and apparatus are provided for performing scene anti-aliasing in a computer graphics system including a rasterizer, a texture mapping subsystem and a frame buffer. The method includes the steps of defining a supersample image buffer and a single sample image buffer, using the rasterizer to render a supersampled image to the supersample image buffer, and using the texture mapping subsystem to downsample the supersample image to the single sample image buffer. The downsampled image in the single sample image buffer is anti-aliased. The supersample image buffer and the single sample image buffer are preferably allocated in the frame buffer. The downsampling operation is preferably performed at the time of double buffer swap.

Abstract: A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

Abstract: A fully mirrored memory system includes at least one split memory bus, with each portion of the split memory bus having active memory and mirror memory. Each portion of the memory bus transfers a portion of the data for a memory transaction. If a memory unit is determined to be defective, one portion of the memory bus may be inactivated for hot swapping of memory, and the system can continue to operate using an active portion of the memory bus.

Abstract: A system and method are provided for directing the flow of data and instructions into at least one functional unit. In one embodiment of a system of components defining a plurality of nodes, a queue network manager (QNM) forming a part of each node, is provided. In this embodiment, the QNM comprises an interface to a network that supports intercommunication among the plurality of nodes, an interface configured to pass messages with a functional unit within the node, a random access memory (RAM) configured to store at least one of a message and a programmable instruction, and logic configured to control an operational aspect of a functional unit based on contents of the programmable instruction.

Abstract: A method and apparatus for managing texture mapping data in a computer graphics system, the computer graphics system including a host computer, primitive rendering hardware and a primitive data path extending between the host computer and the primitive rendering hardware. The host computer passes primitives to be rendered by the system to the primitive rendering hardware over the primitive data path. The host computer has a main memory that stores texture mapping data corresponding to the primitives to be rendered. The primitive rendering hardware includes a local texture memory that locally stores the texture mapping data corresponding to at least one of the primitives to be rendered. When a primitive passed to the primitive rendering hardware is to be rendered, a determination is made as to whether its corresponding texture mapping data is in the local texture memory.

Abstract: The present invention is broadly directed to a system of components defining a plurality of nodes and a random access memory (RAM) connected to each node. The system comprises at least one producer functional unit configured to perform a predetermined processing function resulting in the creation of at least one producer message, a communication mechanism configured to manage and control communication of messages with other nodes, at least one pointer that is configurable to point to a storage location within the RAM, and a message logic configured to interpret content of the at least one producer message, the message logic further configured to associate the producer message with a subset of the at least one pointers based upon the content of the at least one producer message, the message logic further configured to store the at least one producer message within the RAM at the locations indicated by the associated subset of at least one pointer.

Abstract: A system is provided for storing pixel data associated with a predetermined pixel region. The system is configured to store pixel data in a predetermined block of memory along with a fill check bit indicative of whether or not values for each pixel within the pixel region are the same as a predetermined reference pixel. The system also provides for the generation of a stream of pixel data corresponding to a pixel region by outputting a value for a pixel within the region that is equal to the reference pixel when the fill check bit is set.

Abstract: A system is provided for processing graphics data and outputting a stream of pixel data for display on an associated display device. The system is configured to store composed pixel data in a predetermined block of memory. The block of memory corresponds to a predetermined scan line of an associated display device.

Abstract: A 3D graphics controller configurable to simultaneously copy portions of a pixel region between a back buffer and a front buffer. The 3D graphics controller includes four memory controllers, each controlling a bank of frame buffer memory. A sequence of addresses defining a pixel region is generated. The addresses are distributed to the four memory controllers according to the memory banks (addresses) coupled thereto. Each memory controller is configured to read pixels according to the addresses and a first offset; and write the pixels according to the addresses and a second offset. The offsets are chosen so as not to shift pixels within the banks. Therefore, each memory controller simultaneously and independently copies a portion of the pixel region without accessing any other memory banks resulting in a copy of the entire pixel region.

Abstract: Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be “tossed” and excluded from any batches currently under construction. The batch building process may then continue without the need for a batch flush responsive to the occurrence of the pixel collision. If the incoming pixel passes the depth comparison, then it may yet be possible to avoid flushing: The current rendering mode of the pipeline is determined. If the current rendering mode does not require read-modify-write operations, then the incoming pixel may be merged with the buffered pixel with which it collides. Merger of the two pixels may be accomplished by overwriting the buffered RGBA pixel components with those of the incoming pixel, but only those components corresponding to asserted bits in the incoming pixel's BEN.