Abstract: Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be “tossed” and excluded from any batches currently under construction. The batch building process may then continue without the need for a batch flush responsive to the occurrence of the pixel collision. If the incoming pixel passes the depth comparison, then it may yet be possible to avoid flushing: The current rendering mode of the pipeline is determined. If the current rendering mode does not require read-modify-write operations, then the incoming pixel may be merged with the buffered pixel with which it collides. Merger of the two pixels may be accomplished by overwriting the buffered RGBA pixel components with those of the incoming pixel, but only those components corresponding to asserted bits in the incoming pixel's BEN.

Abstract: A method and apparatus for controlling access to a multi-bank memory system. Multiple bank/row activation requests are presented by processes or systems seeking access to the memory. One of the banks of the memory is selected to be the target of a next bank/row activation request. Then, one of the requests corresponding to the chosen bank is selected and issued as the next request. Requests may be conditionally and iteratively selected until one is found whose target row corresponds to a currently active row in the target bank.

Abstract: A modified aggressive precharge method and apparatus for controlling a DRAM or system of DRAMs. Groups of memory access commands are sent to a DRAM controller. A bank/row activate command indicator is associated with the beginning of each group, and a bank precharge command indicator is associated with the end of each group. Normally, the DRAM controller will close the bank/row corresponding to a group responsive to the bank precharge command indicator associated with the end of the group; but the DRAM controller may conditionally leave the bank/row open, as follows: The DRAM controller analyzes the command stream to determine whether first and second groups of memory access commands are directed to the same row and bank. If so, then the precharge command indicated at the end of the first group and the activate command indicated at the beginning of the second group are not executed. The effect is to leave the bank/row of the first group open so that the second group may access it without having to reopen it.

Abstract: A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

Abstract: A method and apparatus for managing texture mapping data in a computer graphics system, the computer graphics system including a host computer, primitive rendering hardware and a primitive data path extending between the host computer and the primitive rendering hardware. The host computer passes primitives to be rendered by the system to the primitive rendering hardware over the primitive data path. The host computer has a main memory that stores texture mapping data corresponding to the primitives to be rendered. The primitive rendering hardware includes a local texture memory that locally stores the texture mapping data corresponding to at least one of the primitives to be rendered. When a primitive passed to the primitive rendering hardware is to be rendered, a determination is made as to whether its corresponding texture mapping data is in the local texture memory.

Abstract: A method and apparatus for managing blocks of data in a data processing system, the data processing system including a host computer and data processing hardware, the host computer having a main memory that stores blocks of data to be processed by the data processing hardware, the data processing hardware including a local memory that locally stores a subset of the blocks of data to be processed by the data processing hardware. When a portion of one of the blocks of data is to be processed by the data processing hardware, a determination is made as to whether the block of data is in the local memory. When the block of data is in the local memory, the portion of the block of data to be processed is read from the local memory. When the block of data is not in the local memory, it is downloaded from the host computer main memory to the data processing hardware. The data processing hardware may generate an interrupt to the host computer with a request to download data.

Abstract: A method and apparatus for managing blocks of data in a data processing system, the data processing system including a host computer and data processing hardware, the host computer having a main memory that stores blocks of data to be processed by the data processing hardware, the data processing hardware including a local memory that locally stores a subset of the blocks of data to be processed by the data processing hardware. When a portion of one of the blocks of data is to be processed by the data processing hardware, a determination is made as to whether the block of data is in the local memory. When the block of data is in the local memory, the portion of the block of data to be processed is read from the local memory. When the block of data is not in the local memory, it is downloaded from the host computer main memory to the data processing hardware. The data processing hardware may generate an interrupt to the host computer with a request to download data.

Abstract: A system and method for allocating data among first and second banks of at least one SDRAM, the data including first, second and third words to be accessed during consecutive read operations. The method includes the following steps: storing the first and third words within the first bank, and storing the second word within the second bank. The texture mapping computer graphics system includes a host computer with a main memory that stores texture data including a plurality of texels, and a local memory that stores at least a portion of the texture data. The local memory includes at least one SDRAM.

Abstract: The present invention provides a converging data pipeline device comprising a first pipeline data path for carrying data, a second pipeline data path for carrying data, a shared pipeline data path which is capable of receiving data from each of the first and second pipeline data paths, and a resending mechanism comprised by the second pipeline data path. The resending mechanism makes a backup copy of at least a portion of the data at a particular location on the second path. Each of the paths comprises a plurality of pipeline stages, each pipeline stage capable of holding data and propagating the data in a direction from a first end of the path toward a second end of the path. The first end of the shared path is in communication with the second ends of the first and second data paths for receiving data from the second ends of the first and second data paths. When the flow of data is suspended along the second path, data is sent down the first path and through the shared path.

Abstract: A method and apparatus for managing texture mapping data in a computer graphics system, the computer graphics system including a host computer, primitive rendering hardware and a primitive data path extending between the host computer and the primitive rendering hardware. The host computer passes primitives to be rendered by the system to the primitive rendering hardware over the primitive data path. The host computer has a main memory that stores texture mapping data corresponding to the primitives to be rendered. The primitive rendering hardware includes a local texture memory that locally stores the texture mapping data corresponding to at least one of the primitives to be rendered. When a primitive passed to the primitive rendering hardware is to be rendered, a determination is made as to whether its corresponding texture mapping data is in the local texture memory.

Abstract: A method and apparatus for implementing a fully associative cache directory that stores X cache tags and responds to N read cache tags simultaneously in a single cache directory access to provide a corresponding cache block index for each of the N read cache tags. The cache directory includes a mini-directory and a main directory. The mini-directory stores M cache tags and corresponding block indexes, wherein M is equal to at least N. The mini-directory is fully associative and simultaneously compares each of the M stored cache tags against each of the N read cache tags. The main directory stores the X cache tags and provides corresponding block indexes. The main directory is fully associative and compares P read cache tags against each of the X cache tags simultaneously, P being less than N. The N read cache tags are initially compared against the mini-directory to provide a block index for each of the N read cache tags that hits in the mini-directory.

Abstract: A method and apparatus allocates and stores texture data in a texture mapping computer graphics system. The data includes at least one series of texture MIP maps. The method includes the following steps: dividing each map of the at least one series of MIP maps into at least two map portions; allocating the map portions of each map into a plurality of equally-sized blocks of data such that portions of maps smaller in size than the size of a block are allocated within a single block; storing the blocks within a main memory of the system; and downloading the blocks at least one block at a time from the main memory to a local memory of the system. The step of downloading includes the step of downloading each block into one of first or second banks of at least one SDRAM.

Abstract: A texture mapping computer graphics system includes a host computer with a main memory that stores texture data including a plurality of texels. A local memory stores at least a portion of the texture data. A local memory access unit, coupled to the local memory, accesses texels from the local memory. A texel data buffer, coupled to the local memory access unit, stores a limited number of texels most recently accessed by the access unit from the local memory. A texel interpolator, coupled to the texel data buffer, reads texels from predefined locations of the texel data buffer. The access unit accesses texels from the local memory only when such texels are unavailable to be re-read from the texel data buffer. A circuit, coupled to the interpolator and the local memory access unit, determines whether a current texel is available to be re-read from the texel data buffer.

Abstract: A method and apparatus for managing texture mapping data in a computer graphics system, the system including a host computer, primitive rendering hardware and a textured primitive data path extending between the host computer and the primitive rendering hardware. The host computer passes textured primitives to be rendered by the system using corresponding texture mapping data to the primitive rendering hardware over the textured primitive data path. The host computer has a main memory that stores texture mapping data corresponding to the textured primitives to be rendered. The primitive rendering hardware includes a local texture memory that locally stores the texture mapping data corresponding to at least one of the textured primitives to be rendered.

Abstract: Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

Abstract: Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

Abstract: A method and apparatus for the storage and retrieval of pixel information, including first and second data portions, is shown to include first and second memory devices each having a random access memory and a shift register, wherein the random access memory includes an on screen section and an off screen section. Pixel information is retrieved from the random access memories in response to control signals and transferred to the shift registers. A controller controls the storage and retrieval of the first data portion in the on screen section of the first memory device, controls the storage and retrieval of the second data portion in the off screen section of the second memory device and generates the control signals so that the first and second data portions are outputted from the shift registers simultaneously.

Abstract: Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

Abstract: Methods and apparatus for rendering graphics primitives to display devices in a computer graphics frame buffer system are disclosed. The methods provide an array of addressable video random access memory (VRAM) chips associated to form the graphics frame buffer. The VRAMs in the frame buffer are addressed with coordinate pixel locations on the display device corresponding to locations of the graphics primitives on the display device. The frame buffer is accessed with a graphics rendered according to arbitrarily shaped tiles containing pixels such that the pixels within the tiles have potentially different VRAM addresses.

Abstract: Methods and apparatus for maximizing column address coherency for serial and parallel port accesses to a dual port frame buffer. Performance of the serial port of the frame buffer is greatly improved by separating the page boundaries in the horizontal direction (i.e., scan line organized), while performance of the parallel port of the frame buffer is enhanced by organizing the page boundaries for rectangular areas of the display. Performance at both ports may be maximized at the same time by organizing the video random access memory (VRAM) into tiles and vertically barrel shifting the scan line data at a fixed interval across the video display. During operation, the serial port output looks like an entire row of data while it has actually output parts of N rows of data from two separate rows of memory chips which are changed at the fixed interval. This approach allows the parallel port to organize columns N times higher in the vertical direction.