Abstract: A multiple-layer interconnect structure in an integrated circuit, is formed using damascene techniques. A first layer interconnect has a first dielectric layer through which at least one first layer conductor extends. A second layer interconnect is then formed on the first layer interconnect. The second layer interconnect also includes a second layer dielectric through which at least one second layer conductor extends. However, the second layer interconnect is created by first forming a thick second later dielectric layer and then reducing the thickness of the second layer dielectric prior to a patterning step. As a result topographical irregularities that may have carried over to the second layer interconnect from the first layer interconnect are removed by providing a substantially planar surface on the second layer dielectric.

Abstract: A method of depositing a premetal dielectric layer involves deposition of a triple premetal dielectric layer in in-situ deposition in a single fabrication tool with each subsequent layer being deposited after a previous layer with no intervening handling step. Thus, no intervening cleaning steps or other intermediate steps are performed.

Abstract: At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.

Abstract: A multipurpose cap layer serves as a bottom anti-reflective coating (BARC) during the formation of a resist mask, a hardmask during subsequent etching processes, a hardened surface during subsequent deposition and planarization processes, and optionally as a diffusion barrier to mobile ions from subsequently deposited materials.

Abstract: An in-situ deposition method allows for the forming of a dielectric layer suitable for use in forming a conductive path in a semiconductor wafer. The method includes depositing a thin SiO.sub.x N.sub.y stop layer on top of a semiconductor wafer within a chemical vapor deposition (CVD) reactor chamber having a low pressure, maintaining the low pressure following the deposition of the SiO.sub.x N.sub.y stop layer, and then depositing a thick TEOS oxide dielectric layer on the SiO.sub.x N.sub.y stop layer within the CVD reactor chamber. The in-situ deposition process reduces outgassing defects that would normally form at the interface between the SiON stop layer and the TEOS oxide dielectric layer.

Abstract: A deposition method allows for the forming of a uniform dielectric stop layer that is substantially void of defects caused by outgassing effects. The stop layer is deposited in a reactor chamber at a higher than normal temperature of at least 480.degree. C. The stop layer is then combined with an overlying dielectric layer to provide an inter-level dielectric structure through which a local interconnect can be formed to provide a conductive path to one or more regions of the underlying semiconductor devices.

Abstract: A local interconnection to a device region in/on a substrate is formed by depositing either silicon oxynitride or silicon oxime as an etch stop layer, at a temperature of less than about 480.degree. C. to increase the hot carrier injection (HCI) lifetime of the resulting semiconductor device. A dielectric layer is then deposited over the etch stop layer and through-holes are etched exposing the etch stop layer using a first etching process. A second etching process is then conducted, which etches through the etch stop layer exposing at least one device region. The resulting through-hole is then filled with conductive material(s) to form a local interconnection.

Abstract: During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. In order to prevent punch-through, the oxide spacers are removed prior to forming an overlying dielectric layer.

Abstract: A holding apparatus, a metal deposition system and a wafer processing method which preserve topographical marks, including those used as alignment targets, on a semiconductor wafer by preventing metal from depositing on such marks during metal deposition. The invention eliminates the need to use window mask and etch techniques to provide replication of topographical marks on a newly formed metal layer when a CMP planarization technique is used prior to metal deposition. As a result, cost, cycle time and yield loss due to the additional window mask and etch steps can be eliminated. The holding apparatus includes a wafer retainer for retaining a wafer which has at least one topographical mark and a clamp ring with at least one tab. The wafer is pressed against the clamp ring by the retainer for securing the wafer in the retainer.

Abstract: A method for forming an alloy film by cooling a substrate during a sputter deposition process. In one embodiment, aluminum-copper (Al-Cu) alloy film is deposited on a substrate while the substrate is maintained at a temperature lower than 100.degree. C. during a sputter deposition process, thereby reducing the precipitation of CuAl.sub.2. The substrate is cooled by pumping a coolant gas through a cooled platen and against the substrate during processing. Subsequent film formation prior to etching is also performed below 100.degree. C. to prevent precipitation of CuAl.sub.2 until the Al-Cu alloy film is etched. Large crystal grains are formed by annealing the substrate after etching.

Abstract: A holding apparatus, a metal deposition system and a wafer processing method which preserve topographical marks, including those used as alignment targets, on a semiconductor wafer by preventing metal from depositing on such marks during metal deposition. The invention eliminates the need to use window mask and etch techniques to provide replication of topographical marks on a newly formed metal layer when a CMP planarization technique is used prior to metal deposition. As a result, cost, cycle time and yield loss due to the additional window mask and etch steps can be eliminated. The holding apparatus includes a wafer retainer for retaining a wafer which has at least one topographical mark and a clamp ring with at least one tab. The wafer is pressed against the clamp ring by the retainer for securing the wafer in the retainer.