Patents by Inventor Darin Edward Gerhart

Darin Edward Gerhart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10698840
    Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of all zeroes is returned in response to an indication of another encryption/decryption method.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: June 30, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Darin Edward Gerhart, Cory Lappi, Daniel Robert Lipps, William Jared Walker
  • Publication number: 20200151044
    Abstract: Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device across a link reset includes transmitting a common target phy address for a plurality of target phys during a first link reset, storing the common target phy address in a non-volatile memory of the data storage device, resetting the target phys, and transmitting the stored common target phy address for the plurality of target phys during a second link reset. In another embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device includes matching a received host address for a plurality of target phys and configuring the plurality of target phys into a wide port for the plurality of target phys with the matched received host address.
    Type: Application
    Filed: January 17, 2020
    Publication date: May 14, 2020
    Inventors: Darin Edward GERHART, Nicholas Edward ORTMEIER, Xin CHEN
  • Patent number: 10649909
    Abstract: A device having a controller configured to execute a range crawler algorithm residing in firmware or hardware and a data table containing one or more range entries (RE's), where each of the RE's is part of a logical block address (LBA) span associated with a command instruction, and where each LBA span has one or more LBA ranges, and where each LBA range is made of one or more sequential LBA's. The device also includes a collision bitmap configured to store data associated with RE collisions between one or more LBA's and a command dispatcher configured to release selected LBA ranges that are not associated with a RE collision. The range crawler algorithm is configured to search the data table to detect collisions between the RE's.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: May 12, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cory Lappi, Darin Edward Gerhart, Nicholas Edward Ortmeier, William Jared Walker
  • Patent number: 10642519
    Abstract: A method and apparatus that provides a solid state drive that analyzes connection performance during I/O operations and is configured to independently modify connection performance based upon user specified input parameters without the need for host computer management.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: May 5, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Darin Edward Gerhart, Nicholas Edward Ortmeier, Mark David Erickson
  • Patent number: 10642764
    Abstract: An input/output device identifies a workload type for a connected host device. The input/output device applies settings for the workload type to affect one or more of a flash translation layer queue depth of the input/output device, a host device data transfer scheduler of the input/output device, and a command status host notification timing by the input/output device to the host device.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: May 5, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Darin Edward Gerhart, Nicholas Edward Ortmeier, Cory Lappi, William Jared Walker
  • Patent number: 10635154
    Abstract: The present disclosure generally relates to a method for intelligent device initiated SAS Phy PM. Using device internal phy characteristics and future phy usage queue, the device determines optimal SAS Phy PM usage based on a predetermined configuration preference of power versus performance. The device achieves optimal SAS Phy PM Usage by implementing a state machine to manage phy PM states and transitions between the PM states. The device state machine includes capabilities to proactively initiate transitions to partial or slumber PM states, start early wake-up from partial or slumber PM states to mask the associated latency impacts of exiting partial or slumber PM states, and selectively reject host requests to enter a partial or slumber PM state.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: April 28, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mark David Erickson, Darin Edward Gerhart, Nicholas Edward Ortmeier, Yasunobu Suginaka
  • Publication number: 20200118585
    Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 16, 2020
    Inventors: Darin Edward GERHART, Nicholas Edward ORTMEIER, Cory LAPPI, William Jared WALKER
  • Publication number: 20200110709
    Abstract: The present disclosure describes logical to physical tables that are configured to provide multiple sector support and provide for help in processing of data when a sector is mapped or unmapped. In the cases where sectors are unmapped, the present disclosure provides mechanisms to concurrently support multiple unique unmapped data patterns depending upon the specific type of unmapped sector.
    Type: Application
    Filed: June 24, 2019
    Publication date: April 9, 2020
    Inventors: Cory LAPPI, William Jared WALKER, Darin Edward GERHART
  • Publication number: 20200065258
    Abstract: A method and arrangement are disclosed involving receiving a read-type command at a data storage arrangement, calculating a command span of the received read-type command and performing a look-up command, through use of a processor, for data located in each extent at a condensed logical block address state table for the read-type command, wherein the condensed logical block address state table describes a logical to physical table and at least one of transmitting data and displaying data related to the read-type command found in the condensed logical block address state table.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 27, 2020
    Inventors: Darin Edward GERHART, Cory LAPPI, Nicholas Edward ORTMEIER, William Jared WALKER
  • Patent number: 10565041
    Abstract: Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device across a link reset includes transmitting a common target phy address for a plurality of target phys during a first link reset, storing the common target phy address in a non-volatile memory of the data storage device, resetting the target phys, and transmitting the stored common target phy address for the plurality of target phys during a second link reset. In another embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device includes matching a received host address for a plurality of target phys and configuring the plurality of target phys into a wide port for the plurality of target phys with the matched received host address.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: February 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Darin Edward Gerhart, Nicholas Edward Ortmeier, Xin Chen
  • Publication number: 20200042192
    Abstract: A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command; populating at least one metadata frame with data based on logical block address latency information; initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.
    Type: Application
    Filed: October 9, 2019
    Publication date: February 6, 2020
    Inventors: Darin Edward GERHART, Nicholas Edward ORTMEIER, Mark David ERICKSON
  • Publication number: 20190394127
    Abstract: Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of managing phys of a data storage target device includes waiting to receive a host address on a target phy and transmitting a target phy address for the target phy after waiting to receive the host address on the target phy. In another embodiment, a method of managing phys of a data storage target device includes configuring a target port comprising a first target phy and reconfiguring the target port comprising a first target phy and a second target phy.
    Type: Application
    Filed: September 9, 2019
    Publication date: December 26, 2019
    Inventors: Darin Edward Gerhart, Nicholas Edward Ortmeier, Xin Chen
  • Publication number: 20190384719
    Abstract: A device having a controller configured to execute a range crawler algorithm residing in firmware or hardware and a data table containing one or more range entries (RE's), where each of the RE's is part of a logical block address (LBA) span associated with a command instruction, and where each LBA span has one or more LBA ranges, and where each LBA range is made of one or more sequential LBA's. The device also includes a collision bitmap configured to store data associated with RE collisions between one or more LBA's and a command dispatcher configured to release selected LBA ranges that are not associated with a RE collision. The range crawler algorithm is configured to search the data table to detect collisions between the RE's.
    Type: Application
    Filed: September 20, 2018
    Publication date: December 19, 2019
    Inventors: Cory LAPPI, Darin Edward GERHART, Nicholas Edward ORTMEIER, William Jared WALKER
  • Publication number: 20190377693
    Abstract: A memory device is provided that includes a memory location configured to store information representing data written using a first encryption/decryption method, a read channel configured to read and decrypt information using a second encryption/decryption method and an apparatus configured to prevent the read channel from reading the memory location using the second encryption/decryption method.
    Type: Application
    Filed: July 31, 2019
    Publication date: December 12, 2019
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: William Jared Walker, Cory Lappi, Darin Edward Gerhart, Daniel Roberts Lipps
  • Patent number: 10466911
    Abstract: A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command; populating at least one metadata frame with data based on logical block address latency information; initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 5, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Darin Edward Gerhart, Nicholas Edward Ortmeier, Mark David Erickson
  • Publication number: 20190310787
    Abstract: A method and apparatus that provides a solid state drive that analyzes connection performance during I/O operations and is configured to independently modify connection performance based upon user specified input parameters without the need for host computer management.
    Type: Application
    Filed: April 6, 2018
    Publication date: October 10, 2019
    Inventors: Darin Edward GERHART, Nicholas Edward ORTMEIER, Mark David ERICKSON
  • Patent number: 10423525
    Abstract: An arrangement is disclosed comprising a memory arrangement configured to store and retrieve data; an interface to allow data to be received and transmitted by the arrangement from a host and a processor configured to dynamically conduct automatic performance tuning for the memory arrangement.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: September 24, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Darin Edward Gerhart, Cory Lappi, Nicholas Edward Ortmeier
  • Patent number: 10425333
    Abstract: Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of managing phys of a data storage target device includes waiting to receive a host address on a target phy and transmitting a target phy address for the target phy after waiting to receive the host address on the target phy. In another embodiment, a method of managing phys of a data storage target device includes configuring a target port comprising a first target phy and reconfiguring the target port comprising a first target phy and a second target phy.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: September 24, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Darin Edward Gerhart, Nicholas Edward Ortmeier, Xin Chen
  • Patent number: 10379747
    Abstract: A method includes receiving, by a hardware controller of a storage device and from a host device, a command to read data from or write data to a non-volatile memory device of the storage device. The method includes, responsive to receiving the command: initializing, by firmware executing at a processor of the hardware controller, a command to retrieve data from or write data to the non-volatile memory device; determining, by circuit logic of the hardware controller, a time indicative of when the firmware initialized the command; determining, by the circuit logic, a time indicative of when the command terminated; and storing, by the circuit logic and at a latency monitoring cache of the storage device, a timestamp associated with the time indicative of when the command was initialized and a timestamp associated with the time indicative of when the command terminated.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 13, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mark David Erickson, Adam Christopher Geml, Darin Edward Gerhart, Nicholas Edward Ortmeier
  • Patent number: 10372627
    Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written is disclosed. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of a predefined or custom code is returned in response to an indication of another encryption/decryption method.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: August 6, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: William Jared Walker, Cory Lappi, Darin Edward Gerhart, Daniel Robert Lipps