Patents by Inventor Darrell D. Truhitte

Darrell D. Truhitte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11145581
    Abstract: A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate extending across a saw street. An encapsulant is deposited over the contact. The substrate is removed to expose the contact and encapsulant. The encapsulant and contact are singulated. In some embodiments, the substrate includes a ridge, and the contact is formed over the ridge.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 12, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.
  • Publication number: 20200365494
    Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.
    Type: Application
    Filed: August 4, 2020
    Publication date: November 19, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. TRUHITTE, Soon Wei WANG, Chee Hiong CHEW
  • Patent number: 10770333
    Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: September 8, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.
  • Patent number: 10770332
    Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: September 8, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.
  • Patent number: 10756006
    Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 25, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, Soon Wei Wang, Chee Hiong Chew
  • Patent number: 10707111
    Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: July 7, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.
  • Patent number: 10529632
    Abstract: A method, in some embodiments, comprises: providing a component having first and second electrical nodes; determining that the component lacks multiple, functional electrical couplings between said first and second nodes; damaging at least part of the component as a result of said determination; and determining, as a result of said damage, that the component is defective.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: January 7, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.
  • Publication number: 20190393127
    Abstract: Implementations of semiconductor packages may include: a heat sink including a plurality of projections extending from a first side of the heat sink and a die having a first side and a second side. The first side of the die may be coupled directly to a second side of the heat sink through a thermally conductive and electrically isolating material. The package may also include one or more interconnects including a solderable metal. The one or more interconnects may be coupled to the second side of the die. The package may also include a molding compound around the die and the one or more interconnects. The molding compound may be directly coupled to the second side of the heat sink.
    Type: Application
    Filed: June 20, 2018
    Publication date: December 26, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Darrell D. TRUHITTE
  • Patent number: 10399756
    Abstract: A carrier tape system, in some embodiments, comprises: a tape; a series of index holes along a length of said tape; a series of pockets along said length; a first series of standoff units along said length; and a second series of standoff units along said length, wherein the series of pockets is positioned between the first series of standoff units and the second series of standoff units, wherein the standoff units create a clearance space between the bottom surfaces of said pockets and the tape when said tape is wound on a reel.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 3, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Darrell D. Truhitte
  • Publication number: 20190198375
    Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
    Type: Application
    Filed: March 5, 2019
    Publication date: June 27, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. TRUHITTE, James P. LETTERMAN, JR.
  • Publication number: 20190198374
    Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
    Type: Application
    Filed: March 5, 2019
    Publication date: June 27, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. TRUHITTE, James P. LETTERMAN, JR.
  • Publication number: 20190198376
    Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
    Type: Application
    Filed: March 5, 2019
    Publication date: June 27, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. TRUHITTE, James P. LETTERMAN, JR.
  • Publication number: 20190122967
    Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. TRUHITTE, Soon Wei WANG, Chee Hiong CHEW
  • Patent number: 10269609
    Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: April 23, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.
  • Publication number: 20190088579
    Abstract: A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate extending across a saw street. An encapsulant is deposited over the contact. The substrate is removed to expose the contact and encapsulant. The encapsulant and contact are singulated. In some embodiments, the substrate includes a ridge, and the contact is formed over the ridge.
    Type: Application
    Filed: November 19, 2018
    Publication date: March 21, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. TRUHITTE, James P. LETTERMAN, JR.
  • Patent number: 10199311
    Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: February 5, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, Soon Wei Wang, Chee Hiong Chew
  • Publication number: 20190013249
    Abstract: A method, in some embodiments, comprises: providing a component having first and second electrical nodes; determining that the component lacks multiple, functional electrical couplings between said first and second nodes; damaging at least part of the component as a result of said determination; and determining, as a result of said damage, that the component is defective.
    Type: Application
    Filed: September 11, 2018
    Publication date: January 10, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. TRUHITTE, James P. LETTERMAN, JR.
  • Publication number: 20190002173
    Abstract: A carrier tape system, in some embodiments, comprises: a tape; a series of index holes along a length of said tape; a series of pockets along said length; a first series of standoff units along said length; and a second series of standoff units along said length, wherein the series of pockets is positioned between the first series of standoff units and the second series of standoff units, wherein the standoff units create a clearance space between the bottom surfaces of said pockets and the tape when said tape is wound on a reel.
    Type: Application
    Filed: September 10, 2018
    Publication date: January 3, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Darrell D. TRUHITTE
  • Patent number: 10163766
    Abstract: A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate extending across a saw street. An encapsulant is deposited over the contact. The substrate is removed to expose the contact and encapsulant. The encapsulant and contact are singulated. In some embodiments, the substrate includes a ridge, and the contact is formed over the ridge.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 25, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.
  • Patent number: 10103072
    Abstract: A method, in some embodiments, comprises: providing a component having first and second electrical nodes; determining that the component lacks multiple, functional electrical couplings between said first and second nodes; damaging at least part of the component as a result of said determination; and determining, as a result of said damage, that the component is defective.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: October 16, 2018
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.