Patents by Inventor Darrell D. Truhitte
Darrell D. Truhitte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11145581Abstract: A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate extending across a saw street. An encapsulant is deposited over the contact. The substrate is removed to expose the contact and encapsulant. The encapsulant and contact are singulated. In some embodiments, the substrate includes a ridge, and the contact is formed over the ridge.Type: GrantFiled: November 19, 2018Date of Patent: October 12, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. Truhitte, James P. Letterman, Jr.
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Publication number: 20200365494Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.Type: ApplicationFiled: August 4, 2020Publication date: November 19, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. TRUHITTE, Soon Wei WANG, Chee Hiong CHEW
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Patent number: 10770333Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.Type: GrantFiled: March 5, 2019Date of Patent: September 8, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. Truhitte, James P. Letterman, Jr.
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Patent number: 10770332Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.Type: GrantFiled: March 5, 2019Date of Patent: September 8, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. Truhitte, James P. Letterman, Jr.
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Patent number: 10756006Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.Type: GrantFiled: December 21, 2018Date of Patent: August 25, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. Truhitte, Soon Wei Wang, Chee Hiong Chew
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Patent number: 10707111Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.Type: GrantFiled: March 5, 2019Date of Patent: July 7, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. Truhitte, James P. Letterman, Jr.
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Patent number: 10529632Abstract: A method, in some embodiments, comprises: providing a component having first and second electrical nodes; determining that the component lacks multiple, functional electrical couplings between said first and second nodes; damaging at least part of the component as a result of said determination; and determining, as a result of said damage, that the component is defective.Type: GrantFiled: September 11, 2018Date of Patent: January 7, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. Truhitte, James P. Letterman, Jr.
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Publication number: 20190393127Abstract: Implementations of semiconductor packages may include: a heat sink including a plurality of projections extending from a first side of the heat sink and a die having a first side and a second side. The first side of the die may be coupled directly to a second side of the heat sink through a thermally conductive and electrically isolating material. The package may also include one or more interconnects including a solderable metal. The one or more interconnects may be coupled to the second side of the die. The package may also include a molding compound around the die and the one or more interconnects. The molding compound may be directly coupled to the second side of the heat sink.Type: ApplicationFiled: June 20, 2018Publication date: December 26, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Darrell D. TRUHITTE
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Patent number: 10399756Abstract: A carrier tape system, in some embodiments, comprises: a tape; a series of index holes along a length of said tape; a series of pockets along said length; a first series of standoff units along said length; and a second series of standoff units along said length, wherein the series of pockets is positioned between the first series of standoff units and the second series of standoff units, wherein the standoff units create a clearance space between the bottom surfaces of said pockets and the tape when said tape is wound on a reel.Type: GrantFiled: September 10, 2018Date of Patent: September 3, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Darrell D. Truhitte
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Publication number: 20190198375Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.Type: ApplicationFiled: March 5, 2019Publication date: June 27, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. TRUHITTE, James P. LETTERMAN, JR.
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Publication number: 20190198374Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.Type: ApplicationFiled: March 5, 2019Publication date: June 27, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. TRUHITTE, James P. LETTERMAN, JR.
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Publication number: 20190198376Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.Type: ApplicationFiled: March 5, 2019Publication date: June 27, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. TRUHITTE, James P. LETTERMAN, JR.
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Publication number: 20190122967Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. TRUHITTE, Soon Wei WANG, Chee Hiong CHEW
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Patent number: 10269609Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.Type: GrantFiled: January 30, 2018Date of Patent: April 23, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. Truhitte, James P. Letterman, Jr.
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Publication number: 20190088579Abstract: A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate extending across a saw street. An encapsulant is deposited over the contact. The substrate is removed to expose the contact and encapsulant. The encapsulant and contact are singulated. In some embodiments, the substrate includes a ridge, and the contact is formed over the ridge.Type: ApplicationFiled: November 19, 2018Publication date: March 21, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. TRUHITTE, James P. LETTERMAN, JR.
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Patent number: 10199311Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.Type: GrantFiled: January 25, 2017Date of Patent: February 5, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. Truhitte, Soon Wei Wang, Chee Hiong Chew
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Publication number: 20190013249Abstract: A method, in some embodiments, comprises: providing a component having first and second electrical nodes; determining that the component lacks multiple, functional electrical couplings between said first and second nodes; damaging at least part of the component as a result of said determination; and determining, as a result of said damage, that the component is defective.Type: ApplicationFiled: September 11, 2018Publication date: January 10, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. TRUHITTE, James P. LETTERMAN, JR.
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Publication number: 20190002173Abstract: A carrier tape system, in some embodiments, comprises: a tape; a series of index holes along a length of said tape; a series of pockets along said length; a first series of standoff units along said length; and a second series of standoff units along said length, wherein the series of pockets is positioned between the first series of standoff units and the second series of standoff units, wherein the standoff units create a clearance space between the bottom surfaces of said pockets and the tape when said tape is wound on a reel.Type: ApplicationFiled: September 10, 2018Publication date: January 3, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Darrell D. TRUHITTE
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Patent number: 10163766Abstract: A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate extending across a saw street. An encapsulant is deposited over the contact. The substrate is removed to expose the contact and encapsulant. The encapsulant and contact are singulated. In some embodiments, the substrate includes a ridge, and the contact is formed over the ridge.Type: GrantFiled: November 21, 2016Date of Patent: December 25, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. Truhitte, James P. Letterman, Jr.
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Patent number: 10103072Abstract: A method, in some embodiments, comprises: providing a component having first and second electrical nodes; determining that the component lacks multiple, functional electrical couplings between said first and second nodes; damaging at least part of the component as a result of said determination; and determining, as a result of said damage, that the component is defective.Type: GrantFiled: August 18, 2016Date of Patent: October 16, 2018Assignee: Semiconductor Components Industries, LLCInventors: Darrell D. Truhitte, James P. Letterman, Jr.