Patents by Inventor Darryl D. Restaino
Darryl D. Restaino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9652729Abstract: A method for managing a metrology system includes receiving a part, identifying, with a processing device, a part type associated with the part, retrieving, with the processing device, test rule logic associated with the part type from a database, retrieving, with the processing device, measurement data associated with the identified part type, processing, with the processing device, the measurement data, applying, with the processing device, the test rule logic to the processed measurement data to determine whether the part should be measured, outputting the part responsive to determining that the part should not be measured, and incrementing, with the processing device, a counter and saving a value of the counter in the database responsive to outputting the part responsive to determining that the part should not be measured.Type: GrantFiled: October 27, 2011Date of Patent: May 16, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William K. Hoffman, Jr., Timothy L. Holmes, Jonathan Levy, Christopher E. Pepe, Darryl D. Restaino, Eric P. Solecky, Roger M. Young
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Publication number: 20130110448Abstract: A method for managing a metrology system includes receiving a part, identifying, with a processing device, a part type associated with the part, retrieving, with the processing device, test rule logic associated with the part type from a database, retrieving, with the processing device, measurement data associated with the identified part type, processing, with the processing device, the measurement data, applying, with the processing device, the test rule logic to the processed measurement data to determine whether the part should be measured, outputting the part responsive to determining that the part should not be measured, and incrementing, with the processing device, a counter and saving a value of the counter in the database responsive to outputting the part responsive to determining that the part should not be measured.Type: ApplicationFiled: October 27, 2011Publication date: May 2, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William K. Hoffman, JR., Timothy L. Holmes, Jonathan Levy, Christopher E. Pepe, Darryl D. Restaino, Eric P. Solecky, Roger M. Young
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Patent number: 7998880Abstract: A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.Type: GrantFiled: July 30, 2007Date of Patent: August 16, 2011Assignees: International Business Machines Corporation, Sony CorporationInventors: Son V. Nguyen, Sarah L. Lane, Eric G. Liniger, Kensaku Ida, Darryl D. Restaino
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Patent number: 7910484Abstract: A method of forming a TEOS oxide layer over an nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer formed on a substrate. The method includes forming the nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer on a top surface and a top side beveled edge proximate to the top surface of a substrate; removing or preventing formation of a carbon-rich layer on a bottom side bevel edge region proximate to a bottom surface of the substrate or converting the carbon-rich layer to nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide; and forming the TEOS oxide layer on the top surface, the top side beveled edge and the bottom side bevel edge region of the substrate.Type: GrantFiled: January 11, 2008Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Chester T. Dziobkowski, Thomas F. Houghton, Emily Kinser, Darryl D. Restaino, Yun-Yu Wang
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Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same
Patent number: 7888741Abstract: A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.Type: GrantFiled: April 19, 2006Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Alfred Grill, Vishnubhai V. Patel, Darryl D. Restaino -
Patent number: 7847402Abstract: A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.Type: GrantFiled: February 20, 2007Date of Patent: December 7, 2010Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing, Ltd, Samsung Electronics Co., LtdInventors: Darryl D. Restaino, Griselda Bonilla, Christos D. Dimitrakopoulos, Stephen M. Gates, Jae H. Kim, Michael W. Lane, Xiao H. Liu, Son V. Nguyen, Thomas M. Shaw, Johnny Widodo
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Patent number: 7820559Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: GrantFiled: June 23, 2008Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Darren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang
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Patent number: 7749892Abstract: An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.Type: GrantFiled: November 29, 2006Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Christos D. Dimitrakopoulos, Son V. Nguyen, Alfred Grill, Satyanarayana V. Nitta, Darryl D. Restaino, Terry A. Spooner
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Patent number: 7737029Abstract: Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 ? to about 50 ? and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water.Type: GrantFiled: March 18, 2008Date of Patent: June 15, 2010Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.Inventors: Jae-hak Kim, Griselda Bonilla, Steven E. Molis, Darryl D. Restaino, Hosadurga Shobha, Johnny Widodo
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Patent number: 7678258Abstract: An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.Type: GrantFiled: July 10, 2003Date of Patent: March 16, 2010Assignee: International Business Machines CorporationInventors: Panayotis Andricacos, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Keith T. Kwietniak, Peter S. Locke, Darryl D. Restaino, Soon-Cheon Seo, Philippe M. Vereecken, Erick G. Walton
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Publication number: 20100028695Abstract: A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.Type: ApplicationFiled: July 30, 2007Publication date: February 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Son V. Nguyen, Sarah L. Lane, Eric G. Liniger, Kensaku Ida, Darryl D. Restaino
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Publication number: 20100009161Abstract: Disclosed is a structure and method for forming a structure including a SiCOH layer having increased mechanical strength. The structure includes a substrate having a layer of dielectric or conductive material, a layer of oxide on the layer of dielectric or conductive material, the oxide layer having essentially no carbon, a graded transition layer on the oxide layer, the graded transition layer having essentially no carbon at the interface with the oxide layer and gradually increasing carbon towards a porous SiCOH layer, and a porous SiCOH (pSiCOH) layer on the graded transition layer, the porous pSiCOH layer having an homogeneous composition throughout the layer. The method includes a process wherein in the graded transition layer, there are no peaks in the carbon concentration and no dips in the oxygen concentration.Type: ApplicationFiled: August 27, 2009Publication date: January 14, 2010Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, APPLIED MATERIALS, INC.Inventors: Daniel C. Edelstein, Alexandros Demos, Stephen M. Gates, Alfred Grill, Steven E. Molis, Vu Ngoc Tran Nguyen, Steven Reiter, Darryl D. Restaino, Kang Sub Yim
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Patent number: 7615482Abstract: Disclosed is a structure and method for forming a structure including a SiCOH layer having increased mechanical strength. The structure includes a substrate having a layer of dielectric or conductive material, a layer of oxide on the layer of dielectric or conductive material, the oxide layer having essentially no carbon, a graded transition layer on the oxide layer, the graded transition layer having essentially no carbon at the interface with the oxide layer and gradually increasing carbon towards a porous SiCOH layer, and a porous SiCOH (pSiCOH) layer on the graded transition layer, the porous pSiCOH layer having an homogeneous composition throughout the layer. The method includes a process wherein in the graded transition layer, there are no peaks in the carbon concentration and no dips in the oxygen concentration.Type: GrantFiled: March 23, 2007Date of Patent: November 10, 2009Assignees: International Business Machines Corporation, Applied Materials, Inc.Inventors: Daniel C. Edelstein, Alexandros Demos, Stephen M. Gates, Alfred Grill, Steven E. Molis, Vu Ngoc Tran Nguyen, Steven Reiter, Darryl D. Restaino, Kang Sub Yim
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Publication number: 20090239374Abstract: Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 ? to about 50 ? and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water.Type: ApplicationFiled: March 18, 2008Publication date: September 24, 2009Inventors: Jae hak Kim, Griselda Bonilla, Steven E. Molis, Darryl D. Restaino, Hosadurga Shobha, Johnny Widodo
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Publication number: 20090181544Abstract: A method of forming a TEOS oxide layer over an nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer formed on a substrate. The method includes forming the nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer on a top surface and a top side beveled edge proximate to the top surface of a substrate; removing or preventing formation of a carbon-rich layer on a bottom side bevel edge region proximate to a bottom surface of the substrate or converting the carbon-rich layer to nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide; and forming the TEOS oxide layer on the top surface, the top side beveled edge and the bottom side bevel edge region of the substrate.Type: ApplicationFiled: January 11, 2008Publication date: July 16, 2009Inventors: Chester T. Dziobkowski, Thomas F. Houghton, Emily Kinser, Darryl D. Restaino, Yun-Yu Wang
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Patent number: 7494938Abstract: A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.Type: GrantFiled: February 5, 2007Date of Patent: February 24, 2009Assignees: International Business Machines Corporation, Sony Corporation, Sony Electronics Inc.Inventors: Son V. Nguyen, Sarah L. Lane, Jia Lee, Kensaku Ida, Darryl D. Restaino, Takeshi Nogami
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Patent number: 7459388Abstract: Methods of forming interconnect structures include forming a first metal wiring pattern on a first dielectric layer and forming a capping layer (e.g., SiCN layer) on the first copper wiring pattern. An adhesion layer is deposited on the capping layer, using a first source gas containing octamethylcyclotetrasilane (OMCTS) at a volumetric flow rate in a range from about 500 sccm to about 700 sccm and a second gas containing helium at a volumetric flow rate in a range from about 1000 to about 3000 sccm. The goal of the deposition step is to achieve an adhesion layer having an internal compressive stress of greater than about 150 MPa therein, so that the adhesion layer is less susceptible to etching/cleaning damage and moisture absorption during back-end processing steps. Additional dielectric and metal layers are then deposited on the adhesion layer.Type: GrantFiled: September 6, 2006Date of Patent: December 2, 2008Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing, Ltd., International Business Machines CorporationInventors: Jaehak Kim, Darryl D. Restaino, Johnny Widodo
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Publication number: 20080254643Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: ApplicationFiled: June 23, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Darren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang
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Publication number: 20080233366Abstract: Disclosed is a structure and method for forming a structure including a SiCOH layer having increased mechanical strength. The structure includes a substrate having a layer of dielectric or conductive material, a layer of oxide on the layer of dielectric or conductive material, the oxide layer having essentially no carbon, a graded transition layer on the oxide layer, the graded transition layer having essentially no carbon at the interface with the oxide layer and gradually increasing carbon towards a porous SiCOH layer, and a porous SiCOH (pSiCOH) layer on the graded transition layer, the porous pSiCOH layer having an homogeneous composition throughout the layer. The method includes a process wherein in the graded transition layer, there are no peaks in the carbon concentration and no dips in the oxygen concentration.Type: ApplicationFiled: March 23, 2007Publication date: September 25, 2008Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, APPLIED MATERIALS, INC.Inventors: Daniel C. Edelstein, Alexandros Demos, Stephen M. Gates, Alfred Grill, Steven E. Molis, Vu Ngoc Tran Nguyen, Steven Reiter, Darryl D. Restaino, Kang Sub Yim
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Publication number: 20080197513Abstract: A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.Type: ApplicationFiled: February 20, 2007Publication date: August 21, 2008Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO LTD., CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Darryl D. Restaino, Griselda Bonilla, Christos D. Dimitrakopoulos, Stephen M. Gates, Jae H. Kim, Michael W. Lane, Xiao H. Liu, Son V. Nguyen, Thomas M. Shaw, Johnny Widodo